Comparison between ADC F1 family and F3 family

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DocID023897 Rev 1

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Comparison between ADC F1 family and F3 family

1.1

STM32 ADC F3 family main features

The ADC F3 family presents several new features as:

•

The queue of context for the injected conversion to allow fast context switching.

•

Three Analog watchdogs per ADC allow very precise monitoring of the converted

voltage of one, some or all selected channels.

•

A programmable Single-ended or differential inputs.

•

The delayed-conversion mode is used to ensure that no ADC data loss will occur

whatever are the application requirements.

•

The self calibration for single-ended and differential input.

1.1.1

Using the ADC in regular conversion

Calibration phase

Calibration is preliminary to all ADC operations. It removes the offset error, which may vary

from one chip to another.

1.

Ensure that ADVREGEN[1:0]=01, and that the ADC voltage regulator startup time has

elapsed.

2.

Ensure that ADEN=0.

3.

Select the input mode for this calibration by setting ADCALDIF=0 (single-ended input)

or ADCALDIF=1 (differential input).

4.

Set ADCAL=1.

5.

Wait until ADCAL=0.

6.

Read the calibration factor from the ADC_CALFACT register.

If the ADC is supposed to convert both single-ended and differential inputs, two calibrations

must be performed, one with ADCALDIF=0 and one with ADCALDIF=1.

1.1.2

ADC channel input mode

ADC channel inputs can be configured in single-ended or differential mode.

Single-ended mode

To configure the ADC channels to single-ended mode, first disable the ADC (ADCAL=0,

JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Select

single-ended input mode by programming DIFSEL[15:1] in the ADC_DIFSEL register.

Note:

If ADC analog input Channel-i is configured in single-ended, the DIFSEL[i] should be kept

cleared.

The analog voltage to be converted for channel “i” is the difference between the external

voltage ADC_INi (positive input) and VREF- (negative input).