AN4228 datasheet(61/90 Pages) STMICROELECTRONICS

61 / 90 page

DocID024110 Rev 5

61/90

AN4228

Firmware migration using the library

4.11

Backup data registers

In STM32F1 series, the Backup data registers are managed through the BKP peripheral,

while in STM32F3 series they are a part of the RTC peripheral (there is no BKP peripheral).

The example below shows how to write to/read from Backup data registers in STM32F1

series:

uint16_t BKPdata = 0;

...

/* Enable APB2 interface clock for PWR and BKP */

_APB1PeriphClockCmd(_APB1Periph_PWR | _APB1Periph_BKP, ENABLE);

/* Enable write access to Backup domain */

PWR_BackupAccessCmd(ENABLE);

/* Write data to Backup data register 1 */

void PWR_EnterSleepMode(uint8_t

PWR_SLEEPEntry);

void PWR_EnterSTOPMode(uint32_t

PWR_Regulator, uint8_t PWR_STOPEntry);

void PWR_EnterSTOPMode(uint32_t

PWR_Regulator, uint8_t PWR_STOPEntry);

void PWR_EnterSTANDBYMode(void);

FlagStatus PWR_GetFlagStatus(uint32_t

PWR_FLAG);

FlagStatus PWR_GetFlagStatus(uint32_t

PWR_FLAG);

void PWR_ClearFlag(uint32_t PWR_FLAG);

Additional Wake-up pins are available on STM32F3 series.

Table 25. STM32F10x and STM32F3xx PWR driver API correspondence (continued)

STM32F10x PWR driver API

STM32F3xx PWR driver API

Color key:

= New function

= Same function, but API was changed

= Function not available (NA)

AN4228 Datasheet(PDF) 61 Page - STMicroelectronics