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UPD77112GC Datasheet(PDF) 49 Page - NEC |
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UPD77112GC Datasheet(HTML) 49 Page - NEC |
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49 / 80 page  Data Sheet U12801EJ4V0DS00 49 µµµµPD77110, 77111, 77112 µPD77110 Serial Interface Timing requirements Parameter Symbol Condition MIN. TYP. MAX. Unit SCK cycle time tcSC 60 ns SCK high-/low-level width twSC 25 ns SCK rise/fall time trtSC 20 ns SOEN setup time tsuSOE 5ns SOEN hold time thSOE 10 ns SIEN setup time tsuSIE 5ns SIEN hold time thSIE 10 ns SI setup time tsuSI 5ns SI hold time thSI 10 ns Switching characteristics Parameter Symbol Condition MIN. TYP. MAX. Unit SORQ output delay time tdSOR 25 ns SORQ hold time thSOR 0ns SO output delay time tdSO 25 ns SO hold time thSO 0ns SIAK output delay time tdSIA 25 ns SIAK hold time thSIA 0ns Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in mind the following points when designing your system: • Reinforce the wiring for power supply and ground (if noise is superimposed on the power and ground lines, it has the same effect as if noise were superimposed on the serial clock). • Shorten the wiring between the device’s SCK1 and SCK2 pins, and clock supply source. • Do not cross the signal lines of the serial clock with any other signal lines. Do not route the serial clock line in the vicinity of a line through which a high alternating current flows. • Supply the clock to the SCK1 and SCK2 pins of the device from the clock source on a one-to- one basis. Do not supply clock to several devices from one clock source. • Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure that the rising and falling of the serial clock waveform are clear. ×× Make sure that the serial clock rises and falls linearly. The serial clock must not bound. Noise must not be superimposed on the serial clock. The serial clock must not rise or fall step-wise. |
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