UPD77112GC datasheet(13/80 Pages) NEC

13 / 80 page

Data Sheet U12801EJ4V0DS00

µµµµPD77110, 77111, 77112

1. PIN FUNCTION

Because the pin numbers differ depending on the package, refer to the diagram of the package to be used.

1.1 Pin Function Description

• Power supply

Pin No.

Pin Name

100-pin

TQFP

80-pin

TQFP

80-pin

FBGA

I/O

Function

Shared by:

IVDD

35, 77, 85

31, 63, 71

A5, A7, J5

−

Power to DSP core (+2.5 V)

−

EVDD

25, 50,

64, 75,

100

10, 20,

40, 50,

60, 80

A1, A9,

E1, E9,

J1, J9

−

Power to I/O pins (+3 V)

−

GND

1, 26, 36,

51, 65,

76, 78, 86

1, 11, 21,

32, 41,

51, 61,

64, 72

A8, B2,

B5, B7,

E2, E8,

H5, H8,

−

Ground

−

• System control

Pin No.

Pin Name

100-pin

TQFP

80-pin

TQFP

80-pin

FBGA

I/O

Function

Shared by:

CLKIN

Input

System clock input

−

CLKOUT

Output

Internal system clock output

−

RESET

Input

Internal system reset signal input

PLL0

−−

Input

PLL1

−−

Input

PLL2

−−

Input

PLL multiple setting input (

µPD77110 only)

•

Determines the PLL multiple at reset as

followings:

PLL2: PLL1: PLL0:

000 : Selects PLL multiple of

×1.

001 : Selects PLL multiple of

×2.

010 : Selects PLL multiple of

×3.

111 : Selects PLL multiple of

×8.

•

These pins have no function on the

µPD77111 and 77112 .

−

WAKEUP

Input

Stop mode release signal input.

•

When this pin is asserted active, the stop

mode is released. The function of this pin

can be activated or deactivated by a mask

option.

•

This pin is always valid on the

µPD77110 .

INT4

UPD77112GC Datasheet(PDF) 13 Page - NEC

UPD77112GC Datasheet(HTML) 13 Page - NEC

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