MAX147ACAP datasheet(5/24 Pages) MAXIM

5 / 24 page

+2.7V, Low-Power, 8-Channel,

Serial 12-Bit ADCs

_______________________________________________________________________________________

Figure 1

__________________________________________Typical Operating Characteristics

(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)

0.5

1024

2048

3072

4096

INTEGRAL NONLINEARITY

vs. CODE

0.3

-0.3

-0.5

-0.1

0.1

0.4

0.2

-0.4

-0.2

CODE

0.50

2.25

2.75

4.25

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

VDD (V)

3.75

5.25

3.25

4.75

MAX146

MAX147

0.10

0.20

0.30

0.40

0.50

0.05

0.15

0.25

0.35

0.45

-60

-20

100

140

INTEGRAL NONLINEARITY

vs. TEMPERATURE

TEMPERATURE (°C)

MAX147

MAX146

VDD = 2.7V

TIMING CHARACTERISTICS

(VDD = +2.7V to +3.6V (MAX146); VDD = +2.7V to +5.25V (MAX147); TA = TMIN to TMAX; unless otherwise noted.)

Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX146—internal reference, offset nulled; MAX147—external reference (VREF = +2.500V), offset nulled.

Note 4: Ground “on” channel; sine wave applied to all “off” channels.

Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6: The common-mode range for the analog inputs is from AGND to VDD.

Note 7: External load should not change during conversion for specified accuracy.

Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note 9: Guaranteed by design. Not subject to production testing.

Note 10: Measured as

|VFS(2.7V) - VFS(VDD, MAX)|.

Internal clock mode only (Note 9)

External clock mode only, Figure 2

External clock mode only, Figure 1

DIN to SCLK Setup

Figure 1

Figure 2

Figure 1

MAX14_ _C/E

CONDITIONS

MAX14_ _M

240

Figure 1

tCSH

240

tSTR

CS Rise to SSTRB Output Disable

240

tSDV

CS Fall to SSTRB Output Enable

240

tSSTRB

SCLK Fall to SSTRB

200

tCL

SCLK Pulse Width Low

200

SCLK Pulse Width High

CS to SCLK Rise Hold

100

tCSS

CS to SCLK Rise Setup

240

tTR

CS Rise to Output Disable

240

tDV

CS Fall to Output Enable

tCH

200

tDO

SCLK Fall to Output Data Valid

tDH

DIN to SCLK Hold

µs

1.5

tACQ

Acquisition Time

tSCK

SSTRB Rise to SCLK Rise

100

tDS

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

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