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ATF-501P8 Datasheet(PDF) 2 Page - AVAGO TECHNOLOGIES LIMITED |
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ATF-501P8 Datasheet(HTML) 2 Page - AVAGO TECHNOLOGIES LIMITED |
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2 / 22 page ![]() 2 ATF-501P8 Absolute Maximum Ratings[1] Absolute Symbol Parameter Units Maximum VDS Drain–Source Voltage[2] V 7 VGS Gate–Source Voltage[2] V -5 to 0.8 VGD Gate Drain Voltage[2] V -5 to 1 IDS Drain Current[2] A 1 IGS Gate Current mA 12 Pdiss Total Power Dissipation[3] W 3.5 Pin max. RF Input Power dBm 30 TCH Channel Temperature °C 150 TSTG Storage Temperature °C -65 to 150 θch_b Thermal Resistance[4] °C/W 23 Notes: 1. Operation of this device in excess of any one of these parameters may cause permanent damage. 2. Assumes DC quiescent conditions. 3. Board (package belly) temperatureTB is 25°C. Derate 43.5 mW/°C for TB > 69.5°C. 4. Channel-to-board thermal resistance measured using 150°C Liquid Crystal Measurement method. Notes: 5. Distribution data sample size is 300 samples taken from 3 different wafers and 3 different lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 6. Measurements are made on production test board, which represents a trade-off between optimal OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements. Figure 1. Typical IV curve (Vgs = 0.01V) per step. Vds (V) 0 6 1 2 3 4 5 800 700 600 500 400 300 200 100 0 Vgs=0.6V Vgs=0.55V Vgs=0.5V Vgs=0.7V Vgs=0.65V Product Consistency Distribution Charts at 2 GHz, 4.5V, 200 mA[5,6] Figure 2. P1dB. P1dB (dBm) 27.5 30.5 28 28.5 29 29.5 30 120 100 80 60 40 20 0 Cpk=1.76 Stdev=0.3 +3 Std –3 Std Figure 3. PAE. PAE (%) 45 85 55 65 75 120 100 80 60 40 20 0 Cpk=1.51 Stdev=3.38 +3 Std –3 Std Figure 4. Gain. GAIN (dB) 13 17 14 15 16 100 80 60 40 20 0 Cpk=1.61 Stdev=0.33 +3 Std –3 Std Figure 5. OIP3. OIP3 (dBm) 42 50 43 44 45 46 47 48 49 100 80 60 40 20 0 Cpk=1.1 Stdev=0.87 +3 Std –3 Std |
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