FOR AUTOMOTIVE BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)

S-8235A Series

Seiko Instruments Inc.

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2. RSTO pin

The RSTO pin outputs a reset signal to the next device. The reset signal is transmitted from the lower device to the

upper device. When "H" is input to the RSTI pin, the S-8235A Series is reset and performs a normal operation. When

inputting "L", the reset operation is released, and a self-test operation is initiated.

The RSTO pin outputs "L" after the 8th clock falling when inputting a clock signal (10 Hz typ.) to the CLKI pin (a1 in

Figure 9

). Thereby, a self-test operation in the next device is initiated.

The RSTO pin outputs "H" when inputting "H" to the RSTI pin (a2 in Figure 9).

3. CLKO pin

The CLKO pin outputs a clock signal to the next device. The clock signal is transmitted from the lower device to the

upper device. The CLKO pin outputs "L" when inputting "L" to the RSTI pin (b1 in Figure 9). After that, the CLKO pin

outputs "H" at the 9th clock or subsequent clocks, and outputs "L" after falling (b2 in Figure 9). Thereby, a clock signal

is input to the next device.

The CLKO pin outputs "H" when inputting "H" to the RSTI pin (b3 in Figure 9).

4. CAO pin

The CAO pin outputs a chip active signal to the next device. The signal is to confirm which device of the S-8235A

Series is in a self-test operation. The chip active signal is transmitted from the upper device to the lower device. The

CAO pin output signal from the 1st clock to the 8th clock is controlled according to a clock signal that is input to the

CLKI pin, and, at the 9th clock or subsequent clocks, it is controlled according to a signal that is input to the CAI pin of

the lower device from the CAO pin of the upper device.

The CAO pin outputs "H" at the 1st clock rising when inputting a clock signal to the CLKI pin after inputting "L" to the

RSTI pin (c1 in Figure 9). Thereby, it is possible to confirm that a self-test operation is performed.

And then, the CAO pin outputs "L" at the 8th clock falling (c2 in Figure 9).

At the 9th clock or subsequent clocks, the CAO pin outputs "H" at the next clock rising when inputting "H" to the CAI

pin (c3 in Figure 9). For this reason, the CAO pin of each device outputs "H" with a delay of 1 clock. Therefore, it is

possible to confirm which device is in a self-test operation if the CAO pin output of the lowest device is monitored.

When a self-test operation is performed in a device of "m" stage, the CAO pin output of the lowest device is as follows.

After that, the CAO pin outputs "L" when inputting "L" to the CAI pin (c4 in Figure 9).

m = 1:

The CAO pin outputs "H" at the 1st clock rising after inputting "L" to the RSTI pin.

m = 2 to 8:

The CAO pin outputs "H" at m clock rising after it outputs "L".

m

≥ 9:

The CAO pin maintains "L" after it outputs "L".

The CAO pin outputs "L" when inputting "H" to the RSTI pin (c5 in Figure 9).

5. VCn Pin (n = 2 to 5)

Figure 9

Figure 9

rising. The time period from when inputting "L" to the RSTI pin until the 1st clock rising and the time period from the 7th

or subsequent clocks.