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S8239B Datasheet(PDF) 6 Page - Seiko Instruments Inc

Part # S8239B
Description  OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
PDF  25 Pages
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Manufacturer  SII [Seiko Instruments Inc]
Direct Link  http://www.sii.co.jp
Logo SII - Seiko Instruments Inc

S8239B Datasheet(HTML) 6 Page - Seiko Instruments Inc

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OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239B Series
Rev.1.1_00
Seiko Instruments Inc.
6
Electrical Characteristics
1. Ta =
+25°C
Table 5
(Ta =
+25°C unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Condition
Test
Circuit
Detection Voltage
Overcurrent 1 detection voltage
VDIOV1
−
VDIOV1
− 0.015
VDIOV1
VDIOV1
+ 0.015
V
1
1
Overcurrent 2 detection voltage
*1 VDIOV2
−
VDIOV2
− 0.100
VDIOV2
VDIOV2
+ 0.100
V
1
1
Overcurrent 3 detection voltage
VDIOV3
Overcurrent 3 detection function
"available"
0.90
1.20
1.50
V
1
1
UVLO detection voltage
VUVLO
−
1.90
2.00
2.10
V
1
1
Release Voltage
Overcurrent release voltage
VRIOV
VDD criteria, VDD = 3.5 V
0.7
1.2
1.5
V
1
1
Input Voltage, Operation Voltage
Operation voltage between
VDD pin and VSS pin
VDSOP
Output logic is determined
*2
1.5
−
8
V
−
−
Current Consumption
Current consumption during
normal operation
IOPE
VDD = 3.5 V, VVM = 0 V
1.0
3.5
7.0
μA
2
2
Current consumption during
power-down
IPDN
VDD = VVM = 1.5 V
−
−
0.1
μA
2
2
Internal Resistance
Internal resistance between
VM pin and VDD pin
RVMD
VDD = 1.8 V, VVM = 0 V
100
300
900
k
Ω
3
3
Output Resistance
DO pin resistance "L"
RDOL
VDD = VVINI = 3.5 V, VDO = 0.5 V
2.5
5
10
k
Ω
4
4
Delay Time
Overcurrent 1 detection delay
time
tDlOV1
−
tDIOV1
× 0.6
tDIOV1
tDIOV1
× 1.4
ms
5
5
Overcurrent 2 detection delay
time
tDlOV2
−
tDIOV2
× 0.6
tDIOV2
tDIOV2
× 1.4
ms
5
5
Overcurrent 3 detection delay
time
tDlOV3
Overcurrent 3 detection function
"available"
168
280
392
μs
5
5
UVLO detection delay time
tUVLO
−
2.94
4.90
6.86
s
5
5
*1. Even if overcurrent 1 detection voltage and overcurrent 2 detection voltage are in the same range, VDIOV1 is lower than
VDIOV2.
*2. It indicates that DO pin output logic is determined.



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