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UCD3138128 Datasheet(PDF) 15 Page - Texas Instruments |
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UCD3138128 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 80 page  0.00 1.00 2.00 3.00 4.00 5.00 6.00 DPWM ADC12 Front-end Control Peak Current Mode Timer Filter Constant Power/Constant Current SCI GIO Module C001 UCD3138128, UCD3138A64 www.ti.com SLUSBZ8A – JUNE 2014 – REVISED SEPTEMBER 2014 8.10 Typical Clock Gating Power Savings The CLKGATECTRL register provides control bits that can enable or disable the clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more. By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled in order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current consumption of the device. The power savings chart displays the power savings per module. For example there are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: UCD3138128 UCD3138A64 |
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