GM1851

LINEAR INTEGRATED CIRCUIT

UNISONIC TECHNOLOGIES CO., LTD

6 of 10

www.unisonic.com.tw

QW-R122-007,B

The UTC GM1851 operates from 26V as set by an internal shunt regulator, D3. In the absence of a fault (If=0) the

feedback path status signal (VS) is correspondingly zero. Under these conditions the capacitor discharge current, I1,

sits quiescently at three times its threshold value, ITH, so that noise induced charge on the timing capacitor will be

rapidly removed. When a fault current, If, is induced in the secondary of the external sense transformer, the

operational amplifier, A1, uses feedback to force a virtual ground at the input as it extracts If. The presence of If

during either half-cycle will cause VS to go high, which in turn changes I1 from 3ITH to ITH. Although ITH discharges

the timing capacitor during both half-cycles of the line, If only charges the capacitor during the half-cycle in which If

exits pin 2. Thus during one half-cycle If-ITH charges the timing capacitor, while during the other half-cycle ITH

discharges it. When the capacitor voltage reaches 17.5V, the latch engages and turns off Q3 permitting I2 to drive

the gate of an SCR.

APPLICATION CIRCUITS

A typical ground fault interrupter circuit is shown in Figure 2. It is designed to operate on 120 VAC line voltage with

5 mA normal fault sensitivity.

A full-wave rectifier bridge and a 15k/2W resistor are used to supply the DC power required by the IC. A 1μF

capacitor at pin 8 used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of

the SCR on either half-cycle. When a fault causes the SCR to trigger, the circuit breaker is energized and line

voltage is removed from the load. At this time no fault current flows and the IC discharge current increases from ITH

to 3ITH ( see Circuit Description and Block Diagram ). This quickly resets both the timing capacitor and the output

latch. At this time the circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault

has been removed. A 1000:1 sense transformer is used to detect the normal fault. The fault current, which is

basically the difference current between the hot and neutral lines, is stepped down by 1000 and fed into the input

pins of the operational amplifier through a 10μF capacitor. The 0.0033μF capacitor between pin 2 and pin 3 and the

200 pF between pins 3 and 4 are added to obtain better noise immunity. The normal fault sensitivity is determined by

the timing capacitor discharging current, ITH. ITH can be calculated by:

7V

÷

2

(1)

At the decision point, the average fault current just equals the threshold current, ITH.

2

×

0.91

(2)

Where If(rms) is the rms input fault current to the operational amp and the factor of 2 is due to the fact that If

charges the timing capacitor only during one half-cycle, while ITH discharges the capacitor continuously. The factor

0.91 converts the rms value to an average value. Combining equations (1) and (2) we have

7V

×

0.91

(3)

For example, to obtain 5mA (rms) sensitivity for the circuit in Figure 2 we have:

5mA

7V

×

0.91

1000

=1.5MΩ

(4)

The correct value for RSET can also be determined from the characteristic curve that plots equation (3). Note that

this is an approximate calculation; the exact value of RSET depends on the specific sense transformer used and

UTC GM1851 tolerances. Inasmuch as UL943 specifies a sensitivity '' window '' of 4mA ~ 6mA, provision should be

made to adjust RSET on a per-product basis.

Independent of setting sensitivity, the desired integration time can be obtained through proper selection of the

timing capacitor, Ct. Due to the large number of variables involved, proper selection of Ct is best done empirically.

The following design example, then should only be used as a guideline.

Assume the goal is to meet UL943 timing requirements. Also assume that worst-case timing occurs during GF1

Start-up (S1 closure) with both a heavy normal fault and a 2Ω grounded neutral fault present. This situation is shown

diagrammatically below.