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MIC284 Datasheet(PDF) 4 Page - Micrel Semiconductor

Part # MIC284
Description  Two-Zone Thermal Supervisor Advance Information
PDF  20 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

MIC284 Datasheet(HTML) 4 Page - Micrel Semiconductor

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MIC284
Micrel
MIC284
4
September 29, 2000
Symbol
Parameter
Condition
Min
Typ
Max
Units
Serial Data I/O Pin (DATA)
V
OL
Low Output Voltage
I
OL = 3mA
0.4
V
Note 6
I
OL = 6mA
0.8
V
V
IL
Low Input Voltage
2.7V
≤ V
DD ≤ 5.5V
0.3V
DD
V
V
IH
High Input Voltage
2.7V
≤ V
DD ≤ 5.5V
0.7V
DD
V
C
IN
Input Capacitance
10
pF
I
LEAK
Input current
±0.01
±1
µA
Serial Clock Input (CLK)
V
IL
Low Input Voltage
2.7V
≤ V
DD ≤ 5.5V
0.3V
DD
V
V
IH
High Input Voltage
2.7V
≤ V
DD ≤ 5.5V
0.7V
DD
V
C
IN
Input Capacitance
10
pF
I
LEAK
Input current
±0.01
±1
µA
Status Output (/INT)
V
OL
Low Output Voltage,
I
OL = 3mA
0.4
V
Note 6
I
OL = 6mA
0.8
V
t
INT
Interrupt Propagation Delay,
from TEMP > T_SET or TEMPx < T_HYSTx
t
CONV+1
µs
Note 7, 8
to INT < V
OL, FQ = 00, RPULLUP = 10kΩ
t
nINT
Interrupt Reset Propagation Delay,
from any register read to /INT > V
OH
1
µs
Note 7
FQ = 00, R
PULLUP = 10kΩ
T_SET0
Default T_SET0 Value
t
POR after VDD > VPOR
81
81
81
°C
T_HYST0
Default T_HYST0 Value
t
POR after VDD > VPOR
76
76
76
°C
T_SET1
Default T_SET1 Value
t
POR after VDD > VPOR
97
97
97
°C
T_HYST1
Default T_HYST1 Value
t
POR after VDD > VPOR
92
92
92
°C
Over-Temperature Output (/CRIT)
V
OL
Low Output Voltage,
I
OL = 3mA
0.4
V
Note 6
I
OL = 6mA
0.8
V
t
CRIT
/CRIT Propagation Delay,
from TEMPx > T_SETx or TEMPx < T_HYSTx
t
CONV+1
µs
Note 7, 8
to INT < V
OL, FQ = 00, RPULLUP = 10kΩ
t
nCRIT
/CRIT Reset Propagation Delay,
from TEMPx < nCRITx to /CRIT > V
OH
1
µs
Note 7
FQ = 00, R
PULLUP = 10kΩ
CRIT1
Default CRIT1 Value
t
POR after VDD > VPOR
97
97
97
°C
nCRIT1
Default nCRIT1 Value
t
POR after VDD > VPOR
92
92
92
°C
Serial Interface Timing (Note 7)
t
1
CLK (Clock) Period
2.5
µs
t
2
Data In Setup Time to CLK High
100
ns
t
3
Data Out Stable After CLK Low
0
ns
t
4
DATA Low Setup Time to CLK Low
start condition
100
ns
t
5
DATA High Hold Time
stop condition
100
ns
After CLK High



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