24LCS52

DS21166B-page 6

Preliminary

© 1996 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately. This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for flow diagram.

FIGURE 5-1:

ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Next

Operation

NO

YES

6.0

WRITE PROTECTION

The 24LCS52 has a software write protect feature that

allows the lower half of the array (addresses 00h - 7Fh)

to be permanently write protected, as well as a WP pin

that can be used to protect the entire array.

6.1

Software Write Protect

The software write protect feature is invoked by writing

to the write protect register. This is done by sending a

command similar to a normal write command. As

shown in Figure 6-1, the write protect register is written

by sending a write command with the slave address set

to 0110 instead of 1010 and the address bits and data

bits are don’t cares. Once the software write protect

register has been written, the device will not acknowl-

edge the 0110 control byte. Once the software write

protect register has been written, the write protec-

tion is enabled and cannot be reversed, even if the

device is powered down.

6.2

Hardware Write Protect

regardless of whether the software write protect regis-

it will prevent the software write protect register from

then write protection is determined by the status of the

software write protect register.

FIGURE 6-1:

SETTING WRITE PROTECT REGISTER

S

P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS

DATA

A

C

K

A

C

K

A

C

K