PIC16CE623-20SLASHSS datasheet(60/108 Pages) MICROCHIP

60 / 108 page

PIC16CE62X

DS40182A-page 60

Preliminary

10.5.1

RB0/INT INTERRUPT

External interrupt on RB0/INT pin is edge triggered:

either rising if INTEDG bit (OPTION<6>) is set, or fall-

ing, if INTEDG bit is clear. When a valid edge appears

on the RB0/INT pin, the INTF bit (INTCON<1>) is set.

This interrupt can be disabled by clearing the INTE

control bit (INTCON<4>). The INTF bit must be cleared

in software in the interrupt service routine before

re-enabling this interrupt. The RB0/INT interrupt can

wake-up the processor from SLEEP, if the INTE bit was

set prior to going into SLEEP. The status of the GIE bit

decides whether or not the processor branches to the

interrupt vector following wake-up. See Section 10.8 for

details on SLEEP and Figure 10-19 for timing of

wake-up from SLEEP through RB0/INT interrupt.

10.5.2

TMR0 INTERRUPT

An overﬂow (FFh

→ 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

enabled/disabled

setting/clearing

T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 7.0.

10.5.3

PORTB INTERRUPT

An input change on PORTB <7:4> sets the RBIF

(INTCON<0>) bit. The interrupt can be enabled/dis-

abled by setting/clearing the RBIE (INTCON<4>) bit.

For operation of PORTB (Section 5.2).

10.5.4

COMPARATOR INTERRUPT

See Section 8.6 for complete description of comparator

interrupts.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF inter-

rupt ﬂag may not get set.

FIGURE 10-16: INT PIN INTERRUPT TIMING

OSC1

CLKOUT

INT pin

INTF ﬂag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

Interrupt Latency

PC+1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC+1)

Inst (PC-1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF ﬂag is sampled here (every Q1).

2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

62X.bk Page 60 Tuesday, March 10, 1998 3:40 PM

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