PIC16F872SLASHSP datasheet(16/160 Pages) MICROCHIP

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PIC16F872

DS30221A-page 16

Preliminary

2.2.2.5

PIR1 REGISTER

The PIR1 register contains the individual flag bits for

the peripheral interrupts.

PIR1 REGISTER (ADDRESS 0Ch)

Note:

Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt bits are clear prior to enabling an

interrupt.

R/W-0

—

ADIF

—

SSPIF

CCP1IF

TMR2IF TMR1IF

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7

bit0

bit 7:

Reserved: Always maintain this bit clear

bit 6:

ADIF: A/D Converter Interrupt Flag bit

= An A/D conversion completed

= The A/D conversion is not complete

bit 5-4:

Reserved: Always maintain this bit clear

bit 3:

SSPIF: Synchronous Serial Port (SSP) Interrupt Flag

= The SSP interrupt condition has occurred, and must be cleared in software before returning from the

interrupt service routine. The conditions that will set this bit are:

SPI

A transmission/reception has taken place.

I2C Slave

A transmission/reception has taken place.

I2C Master

A transmission/reception has taken place.

The initiated start condition was completed by the SSP module.

The initiated stop condition was completed by the SSP module.

The initiated restart condition was completed by the SSP module.

The initiated acknowledge condition was completed by the SSP module.

A start condition occurred while the SSP module was idle (Multimaster system).

A stop condition occurred while the SSP module was idle (Multimaster system).

= No SSP interrupt condition has occurred.

bit 2:

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare Mode

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

= TMR2 to PR2 match occurred (must be cleared in software)

= No TMR2 to PR2 match occurred

bit 0:

TMR1IF: TMR1 Overflow Interrupt Flag bit

= TMR1 register overflowed (must be cleared in software)

= TMR1 register did not overflow

PIC16F872/SP Datasheet(PDF) 16 Page - Microchip Technology

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