PIC16F872SLASHSP datasheet(20/160 Pages) MICROCHIP

20 / 160 page

PIC16F872

DS30221A-page 20

Preliminary

2.3

PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The upper bits (PC<12:8>) are not

readable, but are indirectly writable through the

PCLATH register. On any reset, the upper bits of the

PC will be cleared. Figure 2-3 shows the two situations

for the loading of the PC. The upper example in the fig-

ure shows how the PC is loaded on a write to PCL

(PCLATH<4:0>

→ PCH). The lower example in the fig-

ure shows how the PC is loaded during a CALL or GOTO

instruction (PCLATH<4:3>

→ PCH).

FIGURE 2-3:

LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256 byte block). Refer to the

application

note,

“Implementing

Table

Read"

(AN556).

2.3.2

STACK

The PIC16CXX family has an 8-level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space and the stack pointer is not

readable or writable. The PC is PUSHed onto the stack

when a CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN,RETLW

or a RETFIE instruction execution.

PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

2.4

Program Memory Paging

The PIC16CXXX architecture is capable of addressing

a continuous 8K word block of program memory. The

CALL

and GOTO instructions provide 11 bits of the

address, which allows branches within any 2K program

memory page. Therefore, the 8K words of program

memory are broken into four pages. Since the

PIC16FC872 has only 2K words of program memory or

one page, additional code is not required to ensure that

the correct page is selected before a CALL or GOTO

instruction is executed. The PCLATH<4:3> bits should

always be maintained as zeros. If a return from a CALL

instruction (or interrupt) is executed, the entire 13-bit

PC is popped off the stack. Manipulation of the

PCLATH is not required for the return instructions.

2.5

Indirect Addressing, INDF and FSR

Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF reg-

ister. Any instruction using the INDF register actually

accesses the register pointed to by the File Select Reg-

ister, FSR. Reading the INDF register itself indirectly

(FSR = ’0’) will read 00h. Writing to the INDF register

indirectly results in a no-operation (although status bits

may be affected). An effective 9-bit address is obtained

by concatenating the 8-bit FSR register and the IRP bit

(STATUS<7>), as shown in Figure 2-4.

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1:

INDIRECT ADDRESSING

movlw

0x20

;initialize pointer

movwf

FSR

;to RAM

clrf

INDF

;clear INDF register

incf

FSR,F

;inc pointer

btfss

FSR,4

;all done?

goto

;no clear next

CONTINUE

;yes continue

PCLATH<4:0>

PCLATH

Instruction with

ALU

GOTO,CALL

Opcode <10:0>

11 10

PCLATH<4:3>

PCH

PCL

PCLATH

PCH

PCL

PCL as

Destination

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that

occur from the execution of the CALL,

RETURN,

RETLW

and RETFIE instruc-

tions or the vectoring to an interrupt

address.

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