PIC18LC658T-ISLASHCL datasheet(67/366 Pages) MICROCHIP

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 2000 Microchip Technology Inc.

Advanced Information

DS30475A-page 67

PIC18CXX8

5.1.2

TABLAT - TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch is used to hold

8-bit data during data transfers between program

memory and data memory.

5.1.3

TBLPTR - TABLE POINTER REGISTER

The Table Pointer (TBLPTR) addresses a byte within

the program memory. The TBLPTR is comprised of

three SFR registers (Table Pointer Upper byte, High

byte

and

Low

byte).

These

three

registers

(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit

wide pointer. The low order 21-bits allow the device to

address up to 2 Mbytes of program memory space. The

22nd bit allows read only access to the Device ID, the

User ID and the Configuration bits.

The table pointer TBLPTR is used by the TBLRD and

TBLWT

instructions. These instructions can update the

TBLPTR in one of four ways based on the table oper-

ation. These operations are shown in Table 5-1.

These operations on the TBLPTR only affect the low

order 21-bits.

TABLE 5-1:

TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Example

Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*-

TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+*

TBLPTR is incremented before the read/write

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