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PIC16LC62B-04/P Datasheet(PDF) 98 Page - Microchip Technology |
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PIC16LC62B-04/P Datasheet(HTML) 98 Page - Microchip Technology |
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98 / 120 page  PIC16C62B/72A DS35008B-page 98 Preliminary © 1998 Microchip Technology Inc. FIGURE 13-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) TABLE 13-10: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. No. Symbol Characteristic Min Typ† Max Units Conditions 70 TssL2scH, TssL2scL SS ↓ to SCK↓ or SCK↑ input TCY —— ns 71 TscH SCK input high time (slave mode) Continuous 1.25TCY + 30 — — ns 71A Single Byte 40 — — ns Note 1 72 TscL SCK input low time (slave mode) Continuous 1.25TCY + 30 — — ns 72A Single Byte 40 — — ns Note 1 73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 — — ns Note 1 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — — ns 75 TdoR SDO data output rise time PIC16CXX —10 25 ns PIC16LCXX 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS ↑ to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time (master mode) PIC16CXX —10 25 ns PIC16LCXX —20 45 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, TscL2doV SDO data output valid after SCK edge PIC16CXX —— 50 ns PIC16LCXX —— 100 ns 82 TssL2doV SDO data output valid after SS ↓ edge PIC16CXX —— 50 ns PIC16LCXX —— 100 ns 83 TscH2ssH, TscL2ssH SS ↑ after SCK edge 1.5TCY + 40 — — ns † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. SS SCK (CKP = 0) SCK (CKP = 1) SDO SDI 70 71 72 82 SDI 74 75, 76 MSb BIT6 - - - - - -1 LSb 77 MSb IN BIT6 - - - -1 LSb IN 80 83 NOTE: Refer to Figure 13-4 for load conditions. |
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