T - 450 ns

284 pF

LM5116WG

SNVS599D – OCTOBER 2008 – REVISED FEBRUARY 2013

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UVLO

An under-voltage lockout pin is provided to disable the regulator without entering shutdown. If the UVLO pin is

pulled below 1.215V, the regulator enters a standby mode of operation with the soft-start capacitor discharged

and outputs disabled, but with the VCC regulator running. If the UVLO input is pulled above 1.215V, the

controller will resume normal operation. A voltage divider from input to ground can be used to set a VIN threshold

to disable the supply in brown-out conditions or for low input faults. The UVLO pin has a 5 µA internal pull up

current that allows this pin to left open if the input under-voltage lockout function is not needed. For applications

which require fast on/off cycling, the UVLO pin with an open collector control signal may be used to ensure

proper start-up sequencing.

The UVLO pin is also used to implement a “hiccup” current limit. If a current limit fault exists for more than 256

consecutive clock cycles, the UVLO pin will be internally pulled down to 200 mV and then released. A capacitor

to ground connected to the UVLO pin will set the timing for hiccup mode current limit. When this feature is used

in conjunction with the voltage divider, a diode across the top resistor may be used to discharge the capacitor in

the event of an input under-voltage condition. There is a 5 µs filter at the input to the fault comparator. At higher

switching frequency (greater than approximately 250 kHz) the hiccup timer may be disabled if the fault capacitor

is not used.

Oscillator and Sync Capability

The LM5116WG oscillator frequency is set by a single external resistor connected between the RT/SYNC pin

and the AGND pin. The resistor should be located very close to the device and connected directly to the pins of

can be calculated from the following equation:

(1)

The LM5116WG oscillator has a maximum programmable frequency that is dependent on the VCC voltage. If

VCC is above 6V, the frequency can be programmed up to 1 MHz. If VCCX is used to bias VCC and VCCX <

6V, the maximum programmable oscillator frequency is 750 kHz.

The RT/SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must

be a higher frequency than the free-running frequency set by the RT resistor. The internal oscillator can be

synchronized to an external clock by AC coupling a positive edge into the RT/SYNC pin. The voltage at the

RT/SYNC pin is nominally 1.215V and must exceed 4V to trip the internal synchronization pulse detection. A 5V

amplitude signal and 100 pF coupling capacitor are recommended. The free-running frequency should be set

nominally 15% below the external clock. Synchronizing above twice the free-running frequency may result in

abnormal behavior of the pulse width modulator.

Error Amplifier and PWM Comparator

The internal high-gain error amplifier generates an error signal proportional to the difference between the

regulated output voltage and an internal precision reference (1.215V). The output of the error amplifier is

connected to the COMP pin allowing the user to provide loop compensation components, generally a type II

network. This network creates a pole at very low frequency, a mid-band zero, and a noise reducing high

frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to

the error amplifier output voltage at the COMP pin.

Ramp Generator

The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the

buck switch current. This switch current corresponds to the positive slope portion of the inductor current. Using

this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides

inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for

PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Also, the

current measurement may introduce significant propagation delays. The filtering, blanking time and propagation

delay limit the minimal achievable pulse width. In applications where the input voltage may be relatively large in

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