PIC17C44-08SLASHP datasheet(124/240 Pages) MICROCHIP

124 / 240 page

PIC17C4X

DS30412C-page 124

INFSNZ

Increment f, skip if not 0

Syntax:

[

label]

INFSNZ f,d

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f) + 1

→ (dest), skip if not 0

Status Affected:

None

Encoding:

0010

010d

ffff

Description:

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

WREG. If 'd' is 1 the result is placed

back in register 'f'.

If the result is not 0, the next instruction,

which is already fetched, is discarded,

and an NOP is executed instead making

it a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

Decode

Read

Execute

Write to

destination

If skip:

Forced NOP

NOP

Execute

NOP

Example:

HERE

INFSNZ

REG, 1

ZERO

NZERO

Before Instruction

REG

After Instruction

REG

REG + 1

If REG

PC =

Address (ZERO)

If REG

PC =

Address (NZERO)

IORLW

Inclusive OR Literal with WREG

Syntax:

[

label ]

IORLW k

Operands:

≤ k ≤ 255

Operation:

(WREG) .OR. (k)

→ (WREG)

Status Affected:

Encoding:

1011

0011

kkkk

Description:

The contents of WREG are OR’ed with

the eight bit literal 'k'. The result is

placed in WREG.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal 'k'

Execute

Write to

WREG

Example:

IORLW

0x35

Before Instruction

WREG

0x9A

After Instruction

WREG

0xBF

PIC17C44-08/P Datasheet(PDF) 124 Page - Microchip Technology

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