PIC17C44-08SLASHP datasheet(125/240 Pages) MICROCHIP

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DS30412C-page 125

PIC17C4X

IORWF

Inclusive OR WREG with f

Syntax:

[

label ]

IORWF

f,d

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(WREG) .OR. (f)

→ (dest)

Status Affected:

Encoding:

0000

100d

ffff

Description:

Inclusive OR WREG with register 'f'. If

'd' is 0 the result is placed in WREG. If

'd' is 1 the result is placed back in regis-

ter 'f'.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Execute

Write to

destination

Example:

IORWF

RESULT, 0

Before Instruction

RESULT =

0x13

WREG

0x91

After Instruction

RESULT =

0x13

WREG

0x93

LCALL

Long Call

Syntax:

[

label ]

LCALL

Operands:

≤ k ≤ 255

Operation:

PC + 1

→ TOS;

→ PCL, (PCLATH) → PCH

Status Affected:

None

Encoding:

1011

0111

kkkk

Description:

LCALL

allows an unconditional subrou-

tine call to anywhere within the 64k pro-

gram memory space.

First, the return address (PC + 1) is

pushed onto the stack. A 16-bit desti-

nation address is then loaded into the

program counter. The lower 8-bits of

the destination address is embedded in

the instruction. The upper 8-bits of PC

is loaded from PC high holding latch,

PCLATH.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal 'k'

Execute

Write

Forced NOP

NOP

Execute

NOP

Example:

MOVLW

HIGH(SUBROUTINE)

MOVPF

WREG, PCLATH

LCALL

LOW(SUBROUTINE)

Before Instruction

SUBROUTINE

16-bit Address

After Instruction

Address (SUBROUTINE)

PIC17C44-08/P Datasheet(PDF) 125 Page - Microchip Technology

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