WTLPO_15 datasheet(2/10 Pages) ETC2

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I SPEC 01 I REV.00 I NOVEMBER 2014

CRYSTALS ∙ OSCILLATORS ∙ CERAMIC RESONATORS ∙ CERAMIC FILTERS ∙ SAW COMPONENTS

PETERMANN-TECHNIK GmbH

Lechwiesenstr. 13 ∙ D-86899 ∙ Landsberg am Lech

Tel: +49/8191/305395 ∙ Fax: +49/8191/305397

info@petermann-technik.com ∙ www.petermann-technik.com

GENERAL DATA[1] (continued)

Note: 1. All electrical specifications in the above table are specified with 15 pF output load and for all VDD(s) unless otherwise stated.

PIN DESCRIPTION

SYMBOL

FUNCTIONALITY

Output Enable

H(3):specified frequency output

L: output is high impedance. Only output driver is disabled.

OE/ ST/NC

Standby

H[3]:specified frequency output

L: output is low (weak pull down).Device goes to sleepmode.

Supply current reduces to I_std.

No connect

Any voltage between 0 and VDD or Open[3]: Specified fre-

quency output. Pin 1 has no function.

GND

Power

Electrical ground[4]

OUT

Output

Oscillator output

VDD

Power

Power supply voltage[4]

Note: 3. In OE or ST mode, a pull-up resistor of 10kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.

4. A capacitor value of 0.1 µF between VDD and GND is required.

GND 2

OE/ST/NC

OUT

VDD

TOP VIEW

PARAMETER AND CONDITIONS

SYMBOL

MIN.

TYP.

MAX.

UNIT

CONDITION

LVCMOS OUTPUT CHARACTERISTICS

Duty Cycle

–

All VDDs

Rise/Fall Time

Tr, Tf

–

1.0

2.0

VDD = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%

–

1.3

2.5

VDD =1.8V, 20% - 80%

–

1.0

3.0

VDD = 2.25V - 3.63V, 20% - 80%

Output High Voltage

VOH

90%

–

VDD

IOH = -4 mA (VDD = 3.0V or 3.3V)

IOH = -3 mA (VDD = 2.8V and VDD= 2.5V)

IOH = -2 mA (VDD= 1.8V)

Output Low Voltage

VOL

–

10%

VDD

IOL = 4 mA (VDD = 3.0V or 3.3V)

IOL = 3 mA (VDD= 2.8V and VDD = 2.5V)

IOL = 2 mA (VDD = 1.8V)

INPUTCHARACTERISTICS

Input High Voltage

VIH

70%

–

VDD

Pin 1, OE or ST

Input Low Voltage

VIL

–

30%

VDD

Pin 1, OE or ST

Input Pull-up Impedence

Z_in

150

kΩ

Pin 1, OE logic high or logic low, or ST logic high

–

MΩ

Pin 1, ST logic low

STARTUP AND RESUME TIMING

Startup Time

T_start

–

Measured from the time VDD reaches 90% of final value

Enable/Disable Time

T_oe

–

130

f = 110 MHz. For other frequencies, T_oe = 100 ns + 3* clock

periods

Resume Time

T_resume

–

Measured from the time ST pin crosses 50% threshold

JITTER

RMS Period Jitter

T_jitt

–

1.6

2.5

f = 75 MHz, VDD = 2.5V, 2.8V, 3.0V or 3.3V

–

1.9

f = 75 MHz, VDD = 1.8V

Peak-to-peak Period Jitter

T_pk

–

f = 75 MHz, VDD = 2.5V, 2.8V, 3.0V or 3.3V

–

f = 75 MHz, VDD = 1.8V

RMS Phase Jitter (random)

T_phj

–

0.5

0.8

f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz

–

1.3

f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz

EXCELLENT RELIABILITY DATA

MTBF

500 million hours

Shock Resistance:

10.000 G

Vibration Resistance:

70 g

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