ML4824CS-2 datasheet(10/16 Pages) MICRO-LINEAR

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ML4824

FUNCTIONAL DESCRIPTION (Continued)

Figure 3. External Component Connections to VCC

No voltage error amplifier is included in the PWM stage

of the ML4824, as this function is generally performed on

the output side of the PWM’s isolation boundary. To

facilitate the design of optocoupler feedback circuitry, an

offset has been built into the PWM’s RAMP 2 input which

allows VDC to command a zero percent duty cycle for

input voltages below 1.25V.

PWM Current Limit

The DC ILIMIT pin is a direct input to the cycle-by-cycle

current limiter for the PWM section. Should the input

voltage at this pin ever exceed 1V, the output of the PWM

will be disabled until the output flip-flop is reset by the

clock pulse at the start of the next PWM power cycle.

VIN OK Comparator

The VIN OK comparator monitors the DC output of the PFC

and inhibits the PWM if this voltage on VFB is less than its

nominal 2.5V. Once this voltage reaches 2.5V, which

corresponds to the PFC output capacitor being charged to

its rated boost voltage, the soft-start begins.

PWM Control (RAMP 2)

When the PWM section is used in current mode, RAMP 2

is generally used as the sampling point for a voltage

representing the current in the primary of the PWM’s

output transformer, derived either by a current sensing

resistor or a current transformer. In voltage mode, it is the

input for a ramp voltage generated by a second set of

timing components (RRAMP2, CRAMP2), which will have a

minimum value of zero volts and should have a peak

value of approximately 5V. In voltage mode operation,

feedforward from the PFC output buss is an excellent way

to derive the timing ramp for the PWM stage.

Soft Start

Start-up of the PWM is controlled by the selection of the

external capacitor at SS. A current source of 50µA supplies

the charging current for the capacitor, and start-up of the

PWM begins at 1.25V. Start-up delay can be programmed

by the following equation:

DELAY

=´ 50

125

(6)

where CSS is the required soft start capacitance, and

tDELAY is the desired start-up delay.

It is important that the time constant of the PWM soft-start

allow the PFC time to generate sufficient output power for

the PWM section. The PWM start-up delay should be at

least 5ms.

Solving for the minimum value of CSS:

Cms

SS =´

125

200

Generating VCC

The ML4824 is a current-fed part. It has an internal shunt

voltage regulator, which is designed to regulate the voltage

internal to the part at 13.5V. This allows a low power

dissipation while at the same time delivering 10V of gate

drive at the PWM OUT and PFC OUT outputs. It is

important to limit the current through the part to avoid

overheating or destroying it. This can be easily done with a

single resistor in series with the Vcc pin, returned to a bias

supply of typically 18V to 20V. The resistor’s value must be

chosen to meet the operating current requirement of the

ML4824 itself (19mA max) plus the current required by the

two gate driver outputs.

EXAMPLE:

With a VBIAS of 20V, a VCC limit of 14.6V (max) and the

ML4824 driving a total gate charge of 110nC at 100kHz

(e.g., 1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate

driver current required is:

IkHz

GATEDRIVE =´

100

(7)

BIAS =

14 6

180

Ω

(8)

To check the maximum dissipation in the ML4824, find

the current at the minimum VCC (12.4V):

CC =

12 4

180

42 2

Ω

(9)

The maximum allowable ICC is 55mA, so this is an

acceptable design.

The ML4824 should be locally bypassed with a 10nF and

a 1

µF ceramic capacitor. In most applications, an

electrolytic capacitor of between 100

µF and 330µF is also

required across the part, both for filtering and as part of

the start-up bootstrap circuitry.

ML4824

VCC

GND

VBIAS

10nF

CERAMIC

1µF

CERAMIC

RBIAS

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