LMZ22005

SNVS686J – MARCH 2011 – REVISED AUGUST 2015

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2) (3)

MIN

MAX

UNIT

VIN to PGND

–0.3

24

V

EN, SYNC to AGND

–0.3

5.5

V

SS/TRK, FB to AGND

–0.3

2.5

V

AGND to PGND

–0.3

0.3

V

Junction temperature

150

°C

Peak reflow case temperature (30 sec)

245

°C

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3)

For soldering specifications, refer to the following document: SNOA549

6.2 ESD Ratings

VALUE

UNIT

Electrostatic

±2000

V

discharge

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VIN

6

20

V

EN, SYNC

0

5

V

Operation junction temperature

–40

125

°C

6.4 Thermal Information

LMZ22005

NDW

UNIT

7 PINS

4-layer Evaluation Printed-Circuit-Board,

19.3

60 vias, No air flow

Junction-to-ambient thermal

°C/W

2-layer JEDEC Printed-Circuit-Board,

21.5

No air flow

Junction-to-case (top) thermal

No air flow

1.9

°C/W

resistance

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2)

Theta JA measured on a 3.5-in × 3.5-in 4-layer board, with 3-oz. copper on outer layers and 2-oz. copper on inner layers, sixty thermal

vias, no air flow, and 1-W power dissipation. Refer to application note layout diagrams.

4

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