AR0331 datasheet(32/72 Pages) ONSEMI

32 / 72 page

AR0331_DS Rev. L Pub. 5/15 EN

©Semiconductor Components Industries, LLC, 2015.

AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor

Sensor PLL

Configure the serial output so that it adheres to the following rules:

• The maximum data-rate per lane (FSERIAL) is 700 Mbps/lane (HiSPi).

• Configure the output pixel rate per lane (CLK_OP) so that the sensor output pixel rate

matches the peak pixel rate (2 x CLK_PIX).

– 4-lane: 4 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 148.5 Mpixel/s)

– 2-lane: 2 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 74.25 Mpixel/s)

– 1-lane: 1 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 37.125 Mpixel/s)

Stream/Standby Control

The sensor supports a soft standby mode. In this mode, the external clock can be option-

ally disabled to further minimize power consumption. If this is done, then the “Power-

Up Sequence” on page 62 must be followed. When the external clock is disabled, the

sensor will be unresponsive to register writes and other operations.

Soft Standby is a low-power state that is controlled through register R0x301A[2]. The

sensor will go to Standby after completion of the current frame readout. When the

sensor comes back from Soft Standby, previously written register settings are still main-

tained. Soft Standby will not occur if the Trigger pin is held high.

A specific sequence needs to be followed to enter and exit from Soft Standby.

Entering Soft Standby:

1. Set R0x301A[12] = 1 if serial mode was used

2. Set R0x301A[2] = 0 and drive Trigger pin low.

Table 12:

PLL Parameters for the Serial Interface

Parameter

Symbol

Min

Max

Unit

External Clock

EXTCLK

MHz

VCO Clock

FVCO

384

768

MHz

Readout Clock

CLK_PIX

74.25

Mpixel/s

Output Clock

CLK_OP

37.125

Mpixel/s

Output Serial Data Rate Per Lane

FSERIAL

300 (HiSPi)

700 (HiSPi)

Mbps

Output Serial Clock Speed Per Lane

FSERIAL_CLK

150 (HiSPi)

350(HiSPi)

MHz

Table 13:

Example PLL Configurations for the Serial Interface

Parameter

4-lane

2-lane

1-lane

Units

16-bit

14-bit

12-bit

10-bit

12-bit

10-bit

FVCO

594

519.75

445.5

742.5

445.5

742.5

MHz

vt_sys_clk_div

vt_pix_clk_div

op_sys_clk_div

op_pix_clk_div

FSERIAL

594

519.75

445.5

371.25

445.5

371.25

MHz

FSERIAL_CLK

297

259.875

222.75

185.63

222.75

185.63

MHz

CLK_PIX

74.25

37.125

18.563

Mpixel/s

CLK_OP

37.125

Mpixel/s

Pixel Rate

148.5

74.25

37.125

Mpixel/s

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