Main

PWM

Auxilary

PWM

Transformer

Current

Trailing Edge

Modulation

Leading Edge

Modulation

Peak Current

Threshold

Peak Current

Threshold

Main

PWM

Auxilary

PWM

Transformer

Current

LM25115

SNVS418A – NOVEMBER 2005 – REVISED APRIL 2013

www.ti.com

Leading edge modulation of the auxiliary PWM controller is required if the main converter is implemented with

peak current mode control. If trailing edge modulation were used, the additional load on the transformer

secondary from the auxiliary channel would be drawn only during the first portion of the phase signal pulse.

Referring to Figure 14, the turn off the high side MOSFET of the auxiliary regulator would create a non-

monotonic negative step in the transformer current. This negative current step would produce instability in a peak

current mode controller. With leading edge modulation, the additional load presented by the auxiliary regulator on

the transformer secondary will be present during the latter portion of the phase signal. This positive step in the

phase signal current can be accommodated by a peak current mode controller without instability.

Figure 14. Leading versus Trailing Edge Modulation

Voltage Mode Control with Current Injection

The LM25115 controller uniquely combines elements and benefits of current mode control in a voltage mode

PWM controller. The current sense amplifier shown in Figure 15 monitors the inductor current as it flows through

a sense resistor connected between CS and VOUT. The voltage gain of the sense amplifier is nominally equal to

16. The current sense output signal is shifted by 1.27V to produce the internal CV reference signal. The CV

signal is applied to the negative input of the PWM comparator and compared to CRMIX as illustrated in

Figure 13. Thus the PWM threshold of the voltage mode controller (CV) varies with the instantaneous inductor

current. Insure that the Vbias voltage is at least 3V above the regulated output voltage (VOUT).

Injecting a signal proportional to the instantaneous inductor current into a voltage mode controller improves the

control loop stability and bandwidth. This current injection eliminates the lead R-C lead network in the feedback

path that is normally required with voltage mode control (see Figure 16). Eliminating the lead network not only

simplifies the compensation, but also reduces sensitivity to output noise that could pass through the lead network

to the error amplifier.

The design of the voltage feedback path through the error amp begins with the selection of R1 and R2 in

Figure 16 to set the regulated output voltage. The steady state output voltage after soft-start is determined by the

following equation:

VOUT(final) = 0.75V x (1+R1/R2)

The parallel impedance of the R1, R2 resistor divider should be approximately 2k

Ω (between 0.5kΩ and 5kΩ).

Lower resistance values may not be properly driven by the error amplifier output and higher feedback resistances

can introduce noise sensitivity. The next step in the design process is selection of R3, which sets the ac gain of

the error amplifier. The ac gain is given by the following equation and should be set to a value less than 30.

GAIN(ac) = R3/(R1|| R2) < 30

The capacitor C1 is connected in series with R3 to increase the dc gain of the voltage regulation loop and

improve output voltage accuracy. The corner frequency set by R3 x C1 should be less than 1/10th of the cross-

over frequency of the overall converter such that capacitor C1 does not add phase lag at the crossover

frequency. Capacitor C2 is added to reduce the noise in the voltage control loop. The value of C2 should be less

than 500pF and C2 may not be necessary with very careful PC board layout.

12

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