ACE25Q200G datasheet(3/46 Pages) ACE

3 / 46 page

ACE25Q200G

2M BIT SPI NOR FLASH Memory Series

VER 1.2

Signal Description

During all operations, VCC must be held stable and within the specified valid range: VCC(min) to

VCC(max).

All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or

VOL, see Section 8.6, DC Electrical Characteristics on page 40). These signals are

Signal Names

Table 1

Pin No

Pin Name

I/O

Description

/CS

Chip Select

SO (IO1)

I/O

Serial Output for single bit data Instructions. IO1 for Dual or Quad

Instructions.

/WP (IO2)

I/O

Write Protect in single bit or Dual data Instructions. IO2 in Quad mode.

The signal has an internal pull-up resistor and may be left unconnected in

the host system if not used for Quad Instructions.

VSS

Ground

SI (IO0)

I/O

Serial Input for single bit data Instructions. IO0 for Dual or Quad

Instructions.

SCLK

Serial Clock

/HOLD# (IO3)

I/O

Hold (pause) serial transfer in single bit or Dual data Instructions. IO3 in

Quad-I/O mode. The signal has an internal pull-up resistor and may be

left unconnected in the host system if not used for Quad Instructions.

VCC

Core and/ O Power Supply

Ordering information

ACE25Q200G UA8

U: Tube

T: Tape and Reel

Pb - free

UA8:USON8 3*2 (0.75mm-0.50mm)

Halogen-free

200:2M bit

ACE25Q200G Datasheet(PDF) 3 Page - ACE Technology Co., LTD.

ACE25Q200G Datasheet(HTML) 3 Page - ACE Technology Co., LTD.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL