MT8889C/MT8889C-1

4-118

Figure 14 - Test Circuits

Figure 15 - Application Notes

TEST POINT

MMD6150 (or

equivalent)

5.0 VDC

2.4 k

Ω

24 k

Ω

130 pF

MMD7000 (or

equivalent)

TEST POINT

5.0 VDC

3 k

Ω

100 pF

Test load for IRQ/CP pin

Test load for D0-D3 pins

INITIALIZATION PROCEDURE

A software reset must be included at the beginning of all programs to initialize the control registers after

power up. The initialization procedure should be implemented 100ms after power up.

Description:

Motorola

Intel

Data

RS0

R/W

WR RD

b3

b2

b1

b0

1) Read Status Register

1

1

1

0

X

X

X

X

2) Write to Control Register

1

0

0

1

0

0

0

0

3) Write to Control Register

1

0

0

1

0

0

0

0

4) Write to Control Register

1

0

0

1

1

0

0

0

5) Write to Control Register

1

0

0

1

0

0

0

0

6) Read Status Register

1

1

1

0

X

X

X

X

TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS

Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.

Sequence:

RS0

R/W

WR RD

b3

b2

b1

b0

1) Write to Control Register A

1

0

0

1

1

1

0

1

(tone out, DTMF, IRQ, Select Control Register B)

2) Write to Control Register B

1

0

0

1

0

0

0

0

(burst mode)

3) Write to Transmit Data Register

0

0

0

1

0

1

1

1

(send a digit 7)

4) Wait for an Interrupt or Poll Status Register

5) Read the Status Register

1

1

1

0

X

X

X

X

-if bit 1 is set, the Tx is ready for the next tone, in which case ...

Write to Transmit Register

0

0

0

1

0

1

0

1

(send a digit 5)

-if bit 2 is set, a DTMF tone has been received, in which case ....

Read the Receive Data Register

0

1

1

0

X

X

X

X

-if both bits are set ...

Read the Receive Data Register

0

1

1

0

X

X

X

X

Write to Transmit Data Register

0

0

0

1

0

1

0

1

NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( ±2 ms) AFTER THE DATA IS

WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)