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MT8889CS Datasheet(PDF) 16 Page - Mitel Networks Corporation

Part # MT8889CS
Description  Integrated DTMFTransceiver with Adaptive Micro Interface
PDF  18 Pages
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Manufacturer  MITEL [Mitel Networks Corporation]
Direct Link  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

MT8889CS Datasheet(HTML) 16 Page - Mitel Networks Corporation

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MT8889C/MT8889C-1
4-122
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration=40 ms. Tone pause=40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the composite signal have an equal amplitude.
6) The tone pair is deviated by ± 1.5 %±2 Hz.
7) Bandwidth limited (3 kHz) Gaussian noise.
8) The precise dial tone frequencies are 350 and 440 Hz (±2 %).
9) Guaranteed by design and characterization. Not subject to production testing.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) For guard time calculation purposes.
Figure 16 - DS/RD/WR Clock Pulse
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (V
SS), unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
Conditions
1DS/RD/WR clock frequency
fCYC
4.0
MHz
Figure 16
2DS/RD/WR cycle period
tCYC
250
ns
Figure 16
3DS/RD/WR low pulse width
tCL
150
ns
Figure 16
4DS/RD/WR high pulse width
tCH
100
ns
Figure 16
5DS/RD/WR rise and fall time
tR,tF
20
ns
Figure 16
6R/W setup time
tRWS
23
ns
Figures 17 & 18
7R/W hold time
tRWH
20
ns
Figures 17 & 18
8
Address setup time (RS0)
tAS
0
ns
Figures 17 - 20
9
Address hold time (RS0)
tAH
40
20
ns
Figures 17 - 20
10
Data hold time (read)
tDHR
22
ns
Figures 17 - 20
11
DS/RD to valid data delay (read)
tDDR
100
ns
Figures 17 - 20
12
Data setup time (write)
tDSW
45
ns
Figures 17 - 20
13
Data hold time (write)
tDHW
10
ns
Figures 17 - 20
14
Chip select setup time
tCSS
45
35
ns
Figures 17 - 20
15
Chip select hold time
tCSH
40
ns
Figures 17 - 20
16
Input Capacitance (data bus)
CIN
5pF
17
Output Capacitance (IRQ/CP)
COUT
5pF
tCYC
tR
tCH
tCL
DS/RD/WR
tF



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