MT9042AP datasheet(5/16 Pages) MITEL

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Preliminary Information

MT9042

3-101

Automatic Mode

In normal AUTOMATIC mode operation, the RSEL

input is set to 0. This will allow the state machine to

control PLL operation and select the reference input

based on the state of the LOSS1 and LOSS2 inputs

(see state transitions in Table 4). If the PRI reference

signal is lost (LOSS1 = HIGH, LOSS2 = LOW), then

the PLL will enter HOLDOVER mode immediately

and stay there for a time determined by the RC time

constant connected to the Guard Time input (GTi,

GTo).

When the primary reference signal has not been

regained and the guard time has been exceeded, the

reference will be switched to SEC.

The

time

constant determined by the RC circuit connected to

the GTi input provides the hysteresis on automatic

switching between PRI and SEC during very short

interruptions of the primary reference signal. The

Guard Time, tgt, can be predicted using the step

response of an RC network. The capacitor voltage

on the RC circuit is described by an exponential

curve. When the capacitor voltage reaches the

positive going threshold of GTi (typically 1.77 volts

for Schmitt trigger TTL inputs, see Figure 4) a logic

HIGH level results. This causes the state machine to

move from the holdover state of PRI to the state of

using SEC as the input reference. The following

equation can be used to determine the Guard Time

tgt:

VGTi

1.77v

time

Figure 4 - a) RC circuit for guard time,

R (

Ω)

C (f)

GTi

GTo

(a)

(b)

b) exponential waveform on GTi

tgt

1.77

–

-------------------------







–

The state machine will continue to monitor the LOSS1

input and will switch back to the PRI reference once

the primary reference becomes functional as indicated

by the LOSS1 input. A logic level HIGH on both the

LOSS1 or LOSS2 inputs indicates that none of the

external

references

are

available.

Under

these

circumstances, the PLL will be switched into the

HOLDOVER state (within a specified rate of frame

slip) until a fuIly functional reference input is available.

Time Interval Error Correction Circuit

(TIE)

The TIE correction circuit generates a virtual input

synchronized

the

selected

primary

input

reference. After a reference rearrangement the TIE

corrects the phase of this new reference in such a

way that the virtual input preserves its phase. In

other words, reference switching will not create

significant phase changes on the virtual input, and

therefore, the outputs of the PLL.

The TIE reset (TRST) aligns the falling edge of the

current input with the falling edge of the primary

input reference. When TRST is held LOW for at least

100 ns, the next falling edge of the reference input

becomes aligned and passes through the TIE circuit

without additional delay.

PLL Measures of Performance

To meet the requirements of AT & T TR62411 and

ETSI 300 011, the following PLL performance

parameters were measured:

•

locking range and lock time

•

slip rate in holdover mode

•

free-run accuracy

•

maximum time interval error and slope

•

intrinsic jitter

•

jitter transfer function

•

output jitter spectrum

•

wander

FSEL

Input Reference Frequency

Reserved

8 kHz

1.544 MHz

2.048 MHz

Table 5 - Input Frequency Selection of the MT9042

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