PDSP16116

10

The butterfly operation

The butterfly operation is the arithmetic operation which is

repeated many times to produce an FFT. The PDSP16116- based

butterfly processor performs this operation in a low power high

accuracy chip set.

A new butterfly operation is commenced each cycle, requir-

ing a new set ot data for B, W, WTA and WTB. Five cycles later,

the corresponding results A

′ and B′ are produced along with

their associated WTOUT. In between, the signals SFTA and

SFTR are produced and acted upon by the shifters in the

PDSP1601/A and PDSP16318/A. The timing of the data and

control signals is shown in Fig.6.

The results (A

′ and B′) of each butterfly calculation in a pass

must be stored to be used later as the input data (A and B) in

the next pass. Each result must be stored together with its as-

sociated word tag, WTOUT. Although WTOUT is common to

both A

′ and B′, it must be stored separately with each word as

the words are used on different cycles during the next pass. At

the inputs, the word tag associated with the A word is known as

WTA and the word tag associated with the B word is known as

WTB. Hence, the WTOUTs from one pass will become the WTAs

and WTBs for the following pass. It should be noted that the first

pass is unique in that word tags need not be input into the but-

terfly as all data initially has the same weighting. Hence, during

the first pass alone, the inputs WTA and WTB are ignored.

Fig. 5 Butterfly operation

Control of the FFT

To enable the block floating point hardware to keep track of

the data, the following signals are provided:

SOBFP

- start of the FFT

EOPSS

- end of current pass

These inform the PDSPl 6116/A when an FFT is starting and

when each pass is complete. Fig.7 shows how these signals

should be used and a commentary is provided below.

be pulled low during the initial cycle when the first data words

A and B are presented to the inputs of the butterfly processor.

remain for the duration of the FFT. New data is presented to the

processor each successive cycle until the end of the first pass

pulled low and held low for a minimum of five cycles, the time

required to clear the pipeline of the butterfly processor so that

all the results from one pass are obtained before beginning the

following pass.

Should a longer pause be required between passes – to ar-

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BR, BI, WR, WI

WTA, WTB

AR, AI

SFTA

SFTR

PR, PI

DAR, DAI

WTOUT

A

′R, A′I, B′R, B′I

Fig. 6 Butterfly data and control signals

FFT Output Normalisation

When an FFT system outputs a series of FFT results for

display, storage or transmission, it is essential that all results

are compatible, i.e. with the binary point in the same position.

However, in order to preserve the dynamic range of the data in

the FFT calculation, the PDSP1601/A employs a range of dif-

ferent weightings. Therefore, data must be re-formatted at the

end of the FFT to the pre-determined common weighting. This

can be done by comparing the exponent of given data word

with the pre-determined universal exponent and then shifting

the data word by the difference. The PDSP1601/A, with its

multifunction 16-bit barrel shifter, is ideally suited to this task.

According to theory, the largest possible data result from an

FFT is N times the largest input data. This means that the bi-

nary point can move a maximum of log

Hence, if the universal exponent is chosen to be log

should give a sufficient range to represent all data points faithfully.

AA

′

BB

′

A

′ = A1BW

B

′ = A2BW

W

be kept low as long as necessary; the next pass cannot com-

mence until it is brought high again. On the initial cycle of each

remain high until the final cycle of that pass, when it is pulled

low again.