VP520S

3

The first video line to be filtered and stored will be derived

from the vertical reference input ( VREF). The user can choose

the number of transitions of the HREF input which must occur,

after VREF has gone active, before starting the filter opera-

tion. Data is then not written to the DRAM until after the

pipeline delay through the filters.

The VP520S only expects to use one field of CCIR601

video, which can be selected by the FREF input or internal

logic. A bit in Control Register 1 ( Internal / External Field

Detect ) determines which option is to be used. An additional

Field Select Bit determines whether the field selected should

correspond to FREF being high or low. When the Field Select

Bit and the input are at the same logical level then that field is

used. Note that FREF transitions must be coincident with

active going VREF transitions.

Internal logic is provided which determines the field ( Field

1 ) in which VREF goes active in less than half a line period

after the HREF input last went active.The half line period is

determined by VREF going active between 1 and 432 CREF

qualified SCLK edges after HREF went active (1-429 in NTSC

mode). Note that coincident VREF and HREF edges will

indicate this field on the first CREF qualified SCLK edge.

This logic is used, rather than the FREF input, when the

Internal / External Field Detect Bit is low. Field 1 is selected

when the Field Select in Control register 1 is low, and Field 2

is used when the bit is high.

In the Split Screen mode this logic is overridden, and both

fields are actually used. External logic is assumed to switch

between two sources of video, one for each field. The internal

DRAM address generator is modified such that half area

pictures from the centre of each source are actually stored as

CIF/QCIF data. The first line used in each field will be 72 line

delays in addition to the number which has been defined by the

user. The split screen option is not supported in the QCIF

mode of operation, and a reset is needed after a mode change

in CIF.

The VP520S will insert zero's into the line delays during

vertical blanking. This ensures that all the filter accumulators

are cleared and the edges of the picture are correctly proc-

essed. The horizontal filters always give the required results

since four decimated values are ignored at either side of the

picture.

Incoming luminance data could have a black level of 16,

which will be shifted if the filter coefficients are not chosen to

exactly give a gain of unity. A Control Bit is thus provided,

which when set causes 16 to be subtracted from incoming

Fig 3 : Macroblock Output Timing

luminance. A black level of zero will then stay as zero through-

out the filter operation. At the output of the filters 16 is always

added to the results, regardless of the state of the Control Bit.

Saturation logic ensures that these addition / subtraction

operations do not produce negative results or values greater

than 254.

A Control Bit is also provided which selects between colour

difference inputs and true Cr Cb chrominance values. Cr Cb

values are 8 bit positive only numbers, with black levels of 128.

These must be converted to two's complement signed num-

bers by subtracting 128, thus giving a black level of zero

through the filters. The outputs of the filters are always

converted to positive only Cr Cb values by adding 128 to the

results, regardless of the state of the Control Bit.

COPING WITH SYNC JITTER

When input syncs to the VP520S have jitter, due to the use

of a composite video decoder which does not produce a line

locked clock, it is necessary to use an external FIFO line

buffer. For this reason the VP520S supports a system in which

external line buffer writes are controlled by the video source

and line reads are controlled by the VP520S. The VP520S in

the decode loop is assumed to be supplying sync to the

VP520S in the encode loop, but the sync generator must be

reset at the start of a frame to be in step with the video source.

Two pins have been supplied to support this situation, namely:

VRST - pin 34, and FRST - pin 36. The falling edge of VRST

(frame start identifier) when FRST (field identifier) is low

identifies the start of the frame. These two inputs can typically

be supplied by the Brooktree Bt812 Composite Video De-

coder. Note that Host Address 3 must be programmed with

the value 02 Hex to enable the reset operation.

CIF/QCIF MACROBLOCK OUTPUTS

When producing decimated CIF/QCIF data in macroblock

format, the device raises a flag when a frame of data is ready

for reading from the frame store ( FSIG ). The FSIG pin is

automatically configured as an output in the decimate mode,

but will only stay active (high) for the time given in Figure 3. If

a Request Macroblock response (REQYUV) is not obtained

during this period, then FSIG will be taken low and the frame

of data presently available will be ignored. It will go high again

when a new frame of data is available.

FSIG

O/P

REQYUV

I/P

20ns

max

10ns

min

First O/P Valid

O/P Valid

MCLK

O/P

DATA

O/P

2ns

min

20ns max

20ns max

20ns max

60 SYSCLK Max , 10SYSCLK Min

Stays high for 11440 (NTSC) or 13284 (PAL) SCLKs if REQYUV not received

20ns max

SYSCLK

33ns min