VP520S

5

necessarily have to have generated two interlaced fields from

the received frame. If the VP520S is receiving frames at the

full CIF 30 Hz frame rate but only displaying PAL frames at 25

Hz, then periodically one of the PAL frames ( comprising two

interlaced fields at 50 Hz ) will be generated from two received

CIF/QCIF frames. An incoming CIF/QCIF frame will always be

used since the interlaced field rate is always greater than 30

Hz in either PAL or NTSC.

The data is read from the frame store such that interpo-

lated data becomes available after programmed delays refer-

enced to the VREF and HREF signals. Six bits are available

to define the line delay, and ten are provided to define the

delay from HREF in CREF periods. The actual delays are

greater than the programmed values because of the internal

pipeline delays, which are also mode dependent.

HREF and VREF can either be user supplied inputs, or are

generated internally from a PAL/NTSC timing generator. A bit

in Control Register 0 determines this option, and when the

internal generator is specified the HREF pin becomes an

output which supplies horizontal sync and the VREF pin

supplies vertical sync. A composite sync output is also pro-

vided for system level use. In this mode the VREF and HREF

signals used internally are effectively vertical and horizontal

sync, and the programmed delays should be chosen to reflect

this condition.

The signals provided from the internal timing generator

allow the VP520S to drive the VP510 Colour Space Converter

and an RGB monitor. Detailed output timing is given in Figure

5. Note that the chrominance order can be changed. Alterna-

tively they can be used to drive off the shelf composite video

encoders.

External chrominance data can have a zero colour differ-

ence value of either 0 or 128. This is defined using the

Chrominance Control Bit.

Where 128 is the zero colour

difference value, 128 will be subtracted from incoming

chrominance data and 128 will be added to output chrominace

data. Output values will be limited to lie in the range 16 to 240.

External luminace data can have a black luminace level of

either 0 or 16. This is defined using the Luminace Control Bit.

Where 16 is the black value, 16 will be subtracted from

incoming luminace data and 16 will be added to output

luminace data. Output values will be limited to lie in the range

16 to 235.

The data stored in the CIF frame store will not contain the

black levels normally present during horizontal and vertical

flyback. This is inserted by the VP520S at the appropriate

times in order to ensure that the correct filter operation occurs

at the edges of the picture. In addition to these black levels

during flyback, a bit in Control Register 1 allows all active video

to be replaced by a fixed colour. This colour is user definable

through YUV values in three registers.

FRAME STORE INTERFACE

All read and write operations to the external DRAM frame

stores are based on the use of fast page mode with 13.5 MHz

CAS cycles. Internally a 54 MHz clock is produced from the

27MHz System clock, and this determines the minimum time

interval which can be used in the generation of pulses and

defining precharge times. Any DRAM used must meet the

timing constraints given in Table 1.

Reading and writing rates dictate the need for a 16 bit data

interface, and line data is re-organized to allow a 16 bit word

to consist of either two luminance values or two chrominance

values. This gives compatibility with the macroblock require-

ments since a sub block is either all chrominance or all

luminance data. Reading or writing macroblock data requires

jumps between pages, but four words can always be read or

written using fast page mode.

Read and write operations must be timeshared to meet the

requirements of the system. This time-sharing is based on the

use of 16 cycles of the 13.5 MHz clock. When reading or

writing line data to the store, 10 cycles are used for eight

words, and six cycles are left free for four exchanges with the

encoder or decoder. The additional cycles are needed when

Trs

Data

Valid

Tri

Tac

Tas

Tah

Thz

Tlz

Tsh

ADDRESS

CHIP

SELECT

READ

STROBE

DATA

OUT

Tws

Data

Valid

Twi

Tds

Tas

Tah

Tdh

Tsh

ADDRESS

CHIP

SELECT

WRITE

STROBE

DATA

IN

Twa

WRITE CYCLE

READ CYCLE

CHARACTERISTIC

Addresss Set Up Time

Address Hold Time

Cip Select Set Up Time

Chip Select Hold Time

Strobe Inactive Time

Data Access Time

Delay to O/P's low Z

Delay to O/P's high Z

CHARACTERISTIC

Addresss Set Up Time

Address Hold Time

Chip Select Set Up Time

Chip Select Hold Time

Strobe Inactive Time

Strobe Active Time

Data Set Up Time

Data Hold Time

NOTE

Ø is the period of the

input clock

SYMBOL

Tas

Tah

Trs

Tsh

Tri

Tac

Tlz

Thz

MIN

10ns

10ns

10ns

2ns

Øns

2Øns

MAX

20 +3Øns

25ns

SYMBOL

Tas

Tah

Tws

Tsh

Twi

Twa

Tds

Tdh

MIN

10ns

10ns

10ns

2ns

1Øns

3Øns

10ns

10ns

MAX

Fig 6 : Host Interface Timing