GD25Q64 datasheet(15/50 Pages) ELM

15 / 50 page

Rev.1.1

50 -

http://www.elm-tech.com

GD25Q64CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash

7.1. Write Enable (WREN)(06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch

(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),

Write Status Register (WRSR) and Erase/Program Security Register command. The Write Enable (WREN)

command sequence: CS# goes low → sending the Write Enable command → CS# goes high.

Command

0 1 2 3 4 5 6 7

06H

CS#

SCLK

High-Z

7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command

sequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset by

following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,

Block Erase, Chip Erase, Erase/Program Security Register and Reset commands.

Command

0 1 2 3 4 5 6 7

04H

CS#

SCLK

High-Z

7.3. Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to

change the system configuration and memory protection schemes quickly without waiting for the typical non-

volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for

Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable

for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status

Figure 2. Write Enable Sequence Diagram

Figure 3. Write Disable Sequence Diagram

GD25Q64 Datasheet(PDF) 15 Page - ELM Electronics