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Z86C08 Datasheet(PDF) 4 Page - Zilog, Inc.

Part # Z86C08
Description  CMOS 8-BIT LOW-COST 1K/2K-ROM MICROCONTROLLERS
PDF  34 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86C08 Datasheet(HTML) 4 Page - Zilog, Inc.

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Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
4
P R E L I M I N A R Y
DS97DZ80502
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper-
ational sections of these specifications is not implied. Ex-
posure to absolute maximum rating conditions for an ex-
tended period may affect device reliability. Total power
dissipation should not exceed 462 mW for the package.
Power dissipation is calculated as follows:
Total Power dissipation = V
DD x [I
DD
– (sum of I
OH
)] + sum of
[(V
DD
– V
OH
) x I
OH
] + sum of (V
0L
x I
0L
).
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Figure 4).
Parameter
Min
Max
Units
Ambient Temperature under Bias
–40
+105
C
Storage Temperature
–65
+150
C
Voltage on any Pin with Respect to V
SS
[Note 1]
–0.7
+12
V
Voltage on V
DD
Pin with Respect to V
SS
–0.3
+7
V
Voltage on Pin 7 with Respect to VSS [Note 2]
–0.7
V
DD+1
V
Total Power Dissipation
462
mW
Maximum Current out of V
SS
84
mA
Maximum Current into V
DD
84
mA
Maximum Current into an Input Pin [Note 3]
–600
+600
µA
Maximum Current into an Open-Drain Pin [Note 4]
–600
+600
µA
Maximum Output Current Sinked by Any I/O Pin
12
mA
Maximum Output Current Sourced by Any I/O Pin
12
mA
Total Maximum Output Current Sinked by Port 2
70
mA
Total Maximum Output Current Sourced by Port 2
70
mA
Notes:
1. This applies to all pins except where otherwise noted. Maximum current into pin must be
±600µA.
2. There is no input protection diode from pin to V
DD.
3. This excludes Pin 6 and Pin 7.
4. Device pin is not at an output Low state.
Figure 4. Test Load Diagram
From Output
Under Test
150 pF



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