TAS5756M datasheet(39/104 Pages) TI1

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TAS5756M

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SLAS988B – JUNE 2014 – REVISED AUGUST 2015

Table 5. PLL Configuration Recommendations

EQUATIONS

DESCRIPTION

fS (kHz)

Sampling frequency

RMLCK

Ratio between sampling frequency and MLCK frequency (MLCK frequency = RMLCK x sampling frequency)

MLCK (MHz)

System master clock frequency at MLCK input (pin 20)

PLL VCO (MHz) PLL VCO frequency as PLLCK in Figure 61

One of the PLL coefficients in Equation 1

PLL REF (MHz)

Internal reference clock frequency which is produced by MLCK / P

M = K × R

The final PLL multiplication factor computed from K and R as described in Equation 1

K = J.D

One of the PLL coefficients in Equation 1

PLL fS

Ratio between fS and PLL VCO frequency (PLL VCO / fS)

DSP fS

Ratio between operating clock rate and fS (PLL fS / NMAC)

NMAC

The clock divider value in Table 3

DSP CLK (MHz) The operating frequency as DSPCK in Figure 61

MOD fS

Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)

MOD f (kHz)

DAC operating frequency as DACCK in

NDAC

DAC clock divider value in Table 3

OSR clock divider value in Table 3 for generating OSRCK in Figure 61. DOSR must be chosen so that MOD fS / DOSR =

DOSR

16 for correct operation.

NCP

NCP (negative charge pump) clock divider value in Table 3

CP f

Negative charge pump clock frequency (fS × MOD fS / NCP)

Percentage of error between PLL VCO / PLL fS and fS (mismatch error).

% Error

•

This value is typically zero but can be non-zero especially when K is not an integer (D is not zero).

•

This value may be non-zero only when the TAS5756M device acts as a master.

The previous equations explain how to calculate all necessary coefficients and controls to configure the PLL.

Table 6 provides for easy reference to the recommended clock divider settings for the PLL as a Master Clock.

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