XC164CS datasheet(67/71 Pages) INFINEON

67 / 71 page

XC164

Derivatives

Timing Parameters

Data Sheet

V2.1, 2003-06

Note: The shaded parameters have been verified by characterization.

They are not 100% tested.

Table 19

External Bus Cycle Timing (Operating Conditions apply)

Parameter

Symbol

Limits

Unit

min.

max.

Output valid delay for:

RD, WR(L/H)

tc10 CC 113

Output valid delay for:

A23

…A16, BHE, ALE

tc11 CC -1

Output valid delay for:

A15

…A0 (on PORT1)

tc12 CC 116

Output valid delay for:

A15

…A0 (on PORT0)

tc13 CC 316

Output valid delay for:

tc14 CC 114

Output valid delay for:

D15

…D0 (write data, mux-mode)

tc15 CC 317

Output valid delay for:

D15

…D0 (write data, demux-mode)

tc16 CC 317

Output hold time for:

RD, WR(L/H)

tc20 CC -3

3ns

Output hold time for:

A23

…A16, BHE, ALE

tc21 CC 0

8ns

Output hold time for:

A15

…A0 (on PORT0)

tc23 CC 1

Output hold time for:

tc24 CC -3

3ns

Output hold time for:

D15

…D0 (write data)

tc25 CC 1

Input setup time for:

READY, D15

…D0 (read data)

tc30 SR 24

–

Input hold time

READY, D15

…D0 (read data)1)

tc31 SR -5

–

Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge

of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read

data can be removed after the rising edge of RD.

XC164CS Datasheet(PDF) 67 Page - Infineon Technologies AG

XC164CS Datasheet(HTML) 67 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Datasheet Download

Link URL