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ADS8319 Datasheet(PDF) 6 Page - Texas Instruments |
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ADS8319 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 36 page  ADS8319 SLAS600B – MAY 2008 – REVISED DECEMBER 2015 www.ti.com 7.3 Timing Requirements All specifications are typical at –40°C to 85°C, +VA = 5 V, and +VBD ≥ 4.5 V, unless otherwise noted. REF FIGURE MIN TYP MAX UNIT SAMPLING AND CONVERSION RELATED tacq Acquisition time 600 ns Figure 50, Figure 52, Figure 53, tcnv Conversion time 1400 ns Figure 55 tcyc Time between conversions 2000 ns t1 Pulse duration, CONVST high Figure 50, Figure 52 10 ns t6 Pulse duration, CONVST low Figure 53, Figure 55, Figure 58 20 ns I/O RELATED tclk SCLK period 20 ns tclkl SCLK low time 9 ns Figure 50, Figure 52, Figure 53, tclkh SCLK high time 9 ns Figure 55, Figure 58, Figure 60 t2 SCLK falling edge to data remains valid 5 ns t3 SCLK falling edge to next data valid delay 16 ns ten Enable time, CONVST or SDI low to MSB valid Figure 50, Figure 53 15 ns Disable time, CONVST or SDI high or last SCLK falling edge Figure 50, Figure 52, Figure 53, tdis 12 ns to SDO 3-state (CS mode) Figure 55 t4 Setup time, SDI valid to CONVST rising edge 5 ns Figure 53, Figure 55 t5 Hold time, SDI valid from CONVST rising edge 5 ns t7 Setup time, SCLK valid to CONVST rising edge 5 ns Figure 58 t8 Hold time, SCLK valid from CONVST rising edge 5 ns 7.4 Timing Requirements All specifications are typical at –40°C to 85°C, +VA = 5 V, and +4.5 V > +VBD ≥ 2.375 V, unless otherwise noted. REF FIGURE MIN TYP MAX UNIT SAMPLING AND CONVERSION RELATED tacq Acquisition time 600 ns Figure 50, Figure 52, Figure 53, tcnv Conversion time 1400 ns Figure 55 tcyc Time between conversions 2000 ns t1 Pulse width CONVST high Figure 50, Figure 52 10 ns t6 Pulse width CONVST low Figure 53, Figure 55, Figure 58 20 ns I/O RELATED tclk SCLK period 30 ns tclkl SCLK low time 13 ns Figure 50, Figure 52, Figure 53, tclkh SCLK high time 13 ns Figure 55, Figure 58, Figure 60 t2 SCLK falling edge to data remains valid 5 ns t3 SCLK falling edge to next data valid delay 24 ns ten CONVST or SDI low to MSB valid Figure 50, Figure 53 22 ns CONVST or SDI high or last SCLK falling edge to SDO 3- Figure 50, Figure 52, Figure 53, tdis 15 ns state (CS mode) Figure 55 t4 SDI valid setup time to CONVST rising edge 5 ns Figure 53, Figure 55 t5 SDI valid hold time from CONVST rising edge 5 ns t7 SCLK valid setup time to CONVST rising edge 5 ns Figure 58 t8 SCLK valid hold time from CONVST rising edge 5 ns 6 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS8319 |
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