LNBH25SPQR datasheet(8/37 Pages) STMICROELECTRONICS

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Application information

LNBH25S

8/37

DocID026736 Rev 2

Figure 2: Tone enable and disable timing (using external waveform)

2.3

Data encoding by external DiSEqC envelope control through

the DSQIN pin

If an external DiSEqC envelope source is available, the internal 22 kHz generator can be

active during the tone transmission by connecting the DiSEqC envelope source to the

DSQIN pin. In this case the I²C tone control bits must be set: EXTM = 0 and TEN = 1. In

this manner, the internal 22 kHz signal is superimposed to the VOUT DC voltage to generate

the LNB output 22 kHz tone. During the period in which the DSQIN is kept high, the internal

control circuit activates the 22 kHz tone output.

The 22 kHz tone on the VOUT pin is active with about 6 µs delay from the DSQIN TTL

signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the

22 kHz TTL signal on DSQIN has expired, refer to Figure 3: "Tone enable and disable

timing (using envelope signal)".

Figure 3: Tone enable and disable timing (using envelope signal)

2.4

LPM (low power mode)

In order to reduce the total power loss, the LNBH25S is provided with the LPM I²C bit that

can be active (LPM=1) in applications where the 22 kHz tone can be disabled for long

periods

. The LPM bit can be set to “1” when the DiSEqC data transmission is not requested

(no 22 kHz tone output is present); the drop voltage across the integrated LDO regulator

(VUP-VOUT) is reduced to 0.6 V typ. and, consequently, the power loss inside the LNBH25S

linear regulator is reduced as well. For example: at 500 mA load, LPM=1 allowing a

minimum LDO dissipated power of 0.3 W typ. It is recommended to set the LP

M bit to “0”

before starting the 22 kHz DiSEqC data transmission; at this condition the drop voltage

across the LDO is kept to 1 V typ. LPM=0 if the LPM function is not used.

2.5

DiSEqC 2.0 implementation

The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC 2.0 interfacing.

The input pin (DETIN) has to be AC coupled to the DiSEqC bus, and extracted PWK data

is available on the DSQOUT pin. To comply with the bi-directional DiSEqC 2.0 bus

hardware requirements, an output RL filter is needed. In order to avoid 22 kHz waveform

~ 6 µs

15 µ s ~ 60 µs

DSQIN

T one

output

GIPG0907141158LM

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