LNBH25S

List of figures

DocID026736 Rev 2

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List of figures

Figure 1: Block diagram ..............................................................................................................................6

Figure 2: Tone enable and disable timing (using external waveform) ........................................................8

Figure 3: Tone enable and disable timing (using envelope signal) ............................................................8

Figure 4: Surge protection circuit ..............................................................................................................10

Figure 5: Pin connection (top view) ..........................................................................................................13

Figure 6: DiSEqC 1.x application circuit ...................................................................................................16

Figure 7: DiSEqC 2.x application circuit ...................................................................................................17

Figure 8: Data validity on the I²C bus .......................................................................................................20

Figure 9: Timing diagram of I²C bus .........................................................................................................20

Figure 10: Acknowledge on the I²C bus....................................................................................................20

Figure 11: Example of writing procedure starting with first data address 0X2 .........................................21

Figure 12: Example of reading procedure starting with first status address 0X0 .....................................22

Figure 13: QFN24L (4x4 mm) package outline ........................................................................................34

Figure 14: QFN24L (4x4 mm) recommended footprint.............................................................................35