M24C64M-FCU datasheet(18/35 Pages) STMICROELECTRONICS

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Instructions

M24C64M-FCU

18/35

DocID028282 Rev 2

5.2

Read operations

After the successful completion of a Read operation, the device internal address counter is

incremented by one, to point to the next byte address.

For the Read instructions, after each byte read (data out), the device waits for an

acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge

during this 9th time, the device terminates the data transfer and switches to its Standby

mode.

Figure 8. Read mode sequences

5.2.1

Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in

Figure 8) but without sending a Stop condition. Then, the bus master sends another Start

condition, and repeats the device select code, with the RW bit set to 1. The device

acknowledges this, and outputs the contents of the addressed byte. The bus master must

not acknowledge the byte, and terminates the transfer with a Stop condition.

M24C64M-FCU Datasheet(PDF) 18 Page - STMicroelectronics