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M95M01-DWDW4TP Datasheet(PDF) 25 Page - STMicroelectronics |
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M95M01-DWDW4TP Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 40 page ![]() DocID023214 Rev 6 25/40 M95M01-A125 M95M01-A145 Instructions 39 Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write cycle which duration is tW (specified in Table 15). The instruction sequence is shown in Figure 15. The instruction is discarded, and is not executed, under the following conditions: • If a Write cycle is already in progress • If the Block Protect bits (BP1,BP0) = (1,1) • If one of the conditions defined in Section 3.4.1: Protocol control is not satisfied. |
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