M95M01-DWDW4TP datasheet(28/40 Pages) STMICROELECTRONICS

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Application design recommendations

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5.3

Cycling with Error Correction Code (ECC)

The Error Correction Code (ECC) is an internal logic function which is transparent for the

SPI communication protocol.

The ECC logic is implemented on each group of four EEPROM bytes(a). Inside a group, if a

single bit out of the four bytes happens to be erroneous during a Read operation, the ECC

detects this bit and replaces it with the correct value. The read reliability is therefore much

improved.

Even if the ECC function is performed on groups of four bytes, a single byte can be

written/cycled independently. In this case, the ECC function also writes/cycles the three

other bytes located in the same group(a). As a consequence, the maximum cycling budget is

defined at group level and the cycling can be distributed over the 4 bytes of the group: the

sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain

below the maximum value defined in Table 9: Cycling performance by groups of 4 bytes.

Example1: maximum cycling limit reached with 1 million cycles per byte

Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group

cycling budget is 4 million cycles.

Example2: maximum cycling limit reached with unequal byte cycling

Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times,

byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million

cycles.

a. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.

M95M01-DWDW4TP Datasheet(PDF) 28 Page - STMicroelectronics