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C165H

Architectural Overview

Data Sheet

2001-04-19

- EXC

C165H peripherals are:

• Two General Purpose Timer Blocks (GPT1 and GPT2)

• An Asynchronous/Synchronous Serial Interface (ASC)

• A High-Speed Synchronous Serial Interface (SSC)

• An IOM-2 Interface (IOM-2)

• A Watchdog Timer (WDT)

• Seven I/O ports with a total of 72 I/O lines

Each peripheral also contains a set of Special Function Registers (SFRs), which control

the functionality of the peripheral and temporarily store intermediate data results. Each

peripheral has an associated set of status flags. Individually selected clock signals are

generated for each peripheral from binary multiples of the CPU clock.

Peripheral Interfaces

The on-chip peripherals generally have two different types of interfaces, an interface to

the CPU and an interface to external hardware. Communication between CPU and

peripherals is performed through Special Function Registers (SFRs) and interrupts. The

SFRs serve as control/status and data registers for the peripherals. Interrupt requests

are generated by the peripherals based on specific events which occur during their

operation (eg. operation complete, error, etc.).

For interfacing with external hardware, specific pins of the parallel ports are used, when

an input or output function has been selected for a peripheral. During this time, the port

pins are controlled by the peripheral (when used as outputs) or by the external hardware

which controls the peripheral (when used as inputs). This is called the 'alternate (input

or output) function' of a port pin, in contrast to its function as a general purpose I/O pin.

Peripheral Timing

Internal operation of CPU and peripherals is based on the CPU clock (fCPU). The on-chip

oscillator derives the CPU clock from the crystal or from the external clock signal. The

clock signal which is gated to the peripherals is independent from the clock signal which

feeds the CPU. During Idle mode the CPU’s clock is stopped while the peripherals

continue their operation. Peripheral SFRs may be accessed by the CPU once per state.

When an SFR is written to by software in the same state where it is also to be modified

by the peripheral, the software write operation has priority. Further details on peripheral

timing are included in the specific sections about each peripheral.

Programming Hints

Access to SFRs

All SFRs reside in data page 3 of the memory space. The following addressing

mechanisms allow to access the SFRs:

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