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PEB2055 Datasheet(PDF) 54 Page - Infineon Technologies AG |
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PEB2055 Datasheet(HTML) 54 Page - Infineon Technologies AG |
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54 / 269 page ![]() PEB 2055 PEF 2055 Detailed Register Description Semiconductor Group 54 CMD1..0 CFI Mode1,0. Defines the actual number and configuration of the CFI ports. where N = number of time slots in a PCM frame CIS1..0 CFI Alternative Input Selection. In CFI mode 1 and 2 CIS1..0 controls the assignment between logical and physical receive pins. In CFI mode 0 and 3 CIS1,0 should be set to 0. CMD1..0 CFI Mode Number of Logical Ports CFI Data Rate [kbit/s] Min. Required CFI Data Rate [kbit/s] Relative to PCM-Data Rate Necessary Reference Clock (RCL) DCL-Output Frequencies CMD1:CSS0 = 0 min. max. 00 0 4 DU (0..3) 128 2048 32N/3 2xDR DR, 2xDR1) 01 1 2 DU (0..1) 128 4096 64N/3 DR DR 10 2 1 DU 128 8192 64N/3 0.5xDR DR 11 3 8 bi (0..7) 128 1024 16N/3 4xDR DR, 2xDR CFI Mode Port 0Port 1Port 2Port 3 DU0 DD0 DU1 DD1 DU2 DD2 DU3 DD3 0 IN0 OUT0 IN1 OUT1 IN2 OUT2 IN3 OUT3 1IN0 CIS0 = 0 OUT0 IN1 CIS1 = 0 OUT1 IN0 CIS0 = 1 tristate IN1 CIS1 = 1 tristate 2IN CIS0 = 0 OUT not active tristate IN CIS0 = 1 tristate not active tristate 3 I/O4 I/O0 I/O5 I/O1 I/O6 I/O2 I/O7 I/O3 |
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