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SN74LVC257APWLE Datasheet(PDF) 13 Page - Texas Instruments |
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SN74LVC257APWLE Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 30 page ![]() VCC Unused Input Input Output Output Input Unused Input SN54LVC257A, SN74LVC257A www.ti.com SCAS294O – JANUARY 1993 – REVISED JUNE 2015 11 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions table. Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1- μF capacitor is recommended. If there are multiple VCC terminals then 0.01-μF or 0.022-μF capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise. The bypass capacitor must be installed as close to the power terminal as possible for the best results. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. 12.2 Layout Example Figure 7. Layout Diagrams Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: SN54LVC257A SN74LVC257A |
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