PEF2015 datasheet(39/84 Pages) INFINEON

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PEF 2015

Registers Summary

Semiconductor Group

12.97

4.2.2

Configurable Interface Registers

4.2.2.1

Configurable Interface Mode Register 1 (CMD1)

Access in demultiplexed

µP-interface mode: read/write

address: 6H

OMDR:RBS = 1

Access in multiplexed

µP-interface mode:

read/write

address: 2CH

Reset value: 00H

CSS

Clock Source Selection.

0…PDC and PFS are used as clock and framing source for the CFI. Clock

and framing signals derived from these sources are output on DCL and

FSC.

1…DCL and FSC are selected as clock and framing source for the CFI.

CSM

CFI-Synchronization Mode.

The rising FSC-edge synchronizes the CFI-frame.

0…FSC is evaluated with every falling edge of DCL.

1…FSC is evaluated with every rising edge of DCL.

Note: If CSS = 0 is selected, CSM and PMOD:PSM must be programmed identical.

CSP1..0

Clock Source Prescaler 1,0.

The clock source frequency is divided according to the following table to

obtain the CFI-reference clock CRCL (refer to figures 10 and 11).

bit 7

bit 0

CSS

CSM

CSP1

CSP0

CMD1

CMD0

CSP1,0

Prescaler Divisor

1.5

not allowed

PEF2015 Datasheet(PDF) 39 Page - Infineon Technologies AG

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