PEF2015 datasheet(54/84 Pages) INFINEON

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PEF 2015

Registers Summary

Semiconductor Group

12.97

4.2.4

Synchronous Transfer Registers

4.2.4.1

Synchronous Transfer Data Register (STDA)

Access in demultiplexed

µP-interface mode: read/write

address: 3H

OMDR:RBS = 0

Access in multiplexed

µP-interface mode:

read/write

address: 06H

Reset value: xxH

The STDA-register buffers the data transferred over the synchronous transfer channel A.

MTDA7 to MTDA0 hold the bits 7 to 0 of the respective time slot. MTDA7 (MSB) is the

bit transmitted/received first, MTDA0 (LSB) the bit transmitted/received last over the

serial interface.

4.2.4.2

Synchronous Transfer Data Register B (STDB)

Access in demultiplexed

µP-interface mode: read/write

address: 4H

OMDR:RBS = 0

Access in multiplexed

µP-interface mode:

read/write

address: 08H

Reset value: xxH

The STDB-register buffers the data transferred over the synchronous transfer channel B.

MTDB7 to MTDB0 hold the bits 7 to 0 of the respective time slot. MTDB7 (MSB) is the

bit transmitted/received first, MTDB0 (LSB) the bit transmitted/received last over the

serial interface.

bit 7

bit 0

MTDA7

MTDA6

MTDA5

MTDA4

MTDA3

MTDA2

MTDA1

MTDA0

bit 7

bit 0

MTDB7

MTDB6

MTDB5

MTDB4

MTDB3

MTDB2

MTDB1

MTDB0

PEF2015 Datasheet(PDF) 54 Page - Infineon Technologies AG

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