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TMS320F28375DPTPS Datasheet(PDF) 39 Page - Texas Instruments

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Part # TMS320F28375DPTPS
Description  Dual-Core Delfino Microcontrollers
PDF  212 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320F28375DPTPS Datasheet(HTML) 39 Page - Texas Instruments

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TMS320F28379D, TMS320F28377D
TMS320F28376D, TMS320F28375D, TMS320F28374D
www.ti.com
SPRS880F – DECEMBER 2013 – REVISED NOVEMBER 2015
4.5
Pin Multiplexing
4.5.1
GPIO Muxed Pins
Table 4-4 shows the GPIO muxed pins. The default for each pin is the GPIO function, secondary functions
can be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The
GPyGMUXn register should be configured prior to the GPyMUXn to avoid transient pulses on GPIO's from
alternate mux selections. Columns not shown and blank cells are reserved GPIO Mux settings.
Table 4-4. GPIO Muxed Pins(1)(2)
GPIO Mux Selection
GPIO Index
0, 4, 8, 12
1
2
3
5
6
7
15
GPyGMUXn.
00b, 01b,
00b
01b
11b
GPIOz =
10b, 11b
GPyMUXn.
00b
01b
10b
11b
01b
10b
11b
11b
GPIOz =
GPIO0
EPWM1A (O)
SDAA (I/OD)
GPIO1
EPWM1B (O)
MFSRB (I/O)
SCLA (I/OD)
GPIO2
EPWM2A (O)
OUTPUTXBAR1 (O)
SDAB (I/OD)
GPIO3
EPWM2B (O)
OUTPUTXBAR2 (O)
MCLKRB (I/O)
OUTPUTXBAR2 (O)
SCLB (I/OD)
GPIO4
EPWM3A (O)
OUTPUTXBAR3 (O)
CANTXA (O)
GPIO5
EPWM3B (O)
MFSRA (I/O)
OUTPUTXBAR3 (O)
CANRXA (I)
GPIO6
EPWM4A (O)
OUTPUTXBAR4 (O)
EXTSYNCOUT (O)
EQEP3A (I)
CANTXB (O)
GPIO7
EPWM4B (O)
MCLKRA (I/O)
OUTPUTXBAR5 (O)
EQEP3B (I)
CANRXB (I)
GPIO8
EPWM5A (O)
CANTXB (O)
ADCSOCAO (O)
EQEP3S (I/O)
SCITXDA (O)
GPIO9
EPWM5B (O)
SCITXDB (O)
OUTPUTXBAR6 (O)
EQEP3I (I/O)
SCIRXDA (I)
GPIO10
EPWM6A (O)
CANRXB (I)
ADCSOCBO (O)
EQEP1A (I)
SCITXDB (O)
UPP-WAIT (I/O)
GPIO11
EPWM6B (O)
SCIRXDB (I)
OUTPUTXBAR7 (O)
EQEP1B (I)
SCIRXDB (I)
UPP-START (I/O)
GPIO12
EPWM7A (O)
CANTXB (O)
MDXB (O)
EQEP1S (I/O)
SCITXDC (O)
UPP-ENA (I/O)
GPIO13
EPWM7B (O)
CANRXB (I)
MDRB (I)
EQEP1I (I/O)
SCIRXDC (I)
UPP-D7 (I/O)
GPIO14
EPWM8A (O)
SCITXDB (O)
MCLKXB (I/O)
OUTPUTXBAR3 (O)
UPP-D6 (I/O)
GPIO15
EPWM8B (O)
SCIRXDB (I)
MFSXB (I/O)
OUTPUTXBAR4 (O)
UPP-D5 (I/O)
GPIO16
SPISIMOA (I/O)
CANTXB (O)
OUTPUTXBAR7 (O)
EPWM9A (O)
SD1_D1 (I)
UPP-D4 (I/O)
GPIO17
SPISOMIA (I/O)
CANRXB (I)
OUTPUTXBAR8 (O)
EPWM9B (O)
SD1_C1 (I)
UPP-D3 (I/O)
GPIO18
SPICLKA (I/O)
SCITXDB (O)
CANRXA (I)
EPWM10A (O)
SD1_D2 (I)
UPP-D2 (I/O)
GPIO19
SPISTEA (I/O)
SCIRXDB (I)
CANTXA (O)
EPWM10B (O)
SD1_C2 (I)
UPP-D1 (I/O)
GPIO20
EQEP1A (I)
MDXA (O)
CANTXB (O)
EPWM11A (O)
SD1_D3 (I)
UPP-D0 (I/O)
GPIO21
EQEP1B (I)
MDRA (I)
CANRXB (I)
EPWM11B (O)
SD1_C3 (I)
UPP-CLK (I/O)
GPIO22
EQEP1S (I/O)
MCLKXA (I/O)
SCITXDB (O)
EPWM12A (O)
SPICLKB (I/O)
SD1_D4 (I)
GPIO23
EQEP1I (I/O)
MFSXA (I/O)
SCIRXDB (I)
EPWM12B (O)
SPISTEB (I/O)
SD1_C4 (I)
GPIO24
OUTPUTXBAR1 (O)
EQEP2A (I)
MDXB (O)
SPISIMOB (I/O)
SD2_D1 (I)
GPIO25
OUTPUTXBAR2 (O)
EQEP2B (I)
MDRB (I)
SPISOMIB (I/O)
SD2_C1 (I)
GPIO26
OUTPUTXBAR3 (O)
EQEP2I (I/O)
MCLKXB (I/O)
OUTPUTXBAR3 (O)
SPICLKB (I/O)
SD2_D2 (I)
GPIO27
OUTPUTXBAR4 (O)
EQEP2S (I/O)
MFSXB (I/O)
OUTPUTXBAR4 (O)
SPISTEB (I/O)
SD2_C2 (I)
GPIO28
SCIRXDA (I)
EM1CS4 (O)
OUTPUTXBAR5 (O)
EQEP3A (I)
SD2_D3 (I)
GPIO29
SCITXDA (O)
EM1SDCKE (O)
OUTPUTXBAR6 (O)
EQEP3B (I)
SD2_C3 (I)
GPIO30
CANRXA (I)
EM1CLK (O)
OUTPUTXBAR7 (O)
EQEP3S (I/O)
SD2_D4 (I)
GPIO31
CANTXA (O)
EM1WE (O)
OUTPUTXBAR8 (O)
EQEP3I (I/O)
SD2_C4 (I)
GPIO32
SDAA (I/OD)
EM1CS0 (O)
GPIO33
SCLA (I/OD)
EM1RNW (O)
GPIO34
OUTPUTXBAR1 (O)
EM1CS2 (O)
SDAB (I/OD)
GPIO35
SCIRXDA (I)
EM1CS3 (O)
SCLB (I/OD)
GPIO36
SCITXDA (O)
EM1WAIT (I)
CANRXA (I)
GPIO37
OUTPUTXBAR2 (O)
EM1OE (O)
CANTXA (O)
GPIO38
EM1A0 (O)
SCITXDC (O)
CANTXB (O)
GPIO39
EM1A1 (O)
SCIRXDC (I)
CANRXB (I)
(1)
I = Input, O = Output, OD = Open Drain
(2)
GPIO Index settings of 9, 10, 11, 13, and 14 are reserved.
Copyright © 2013–2015, Texas Instruments Incorporated
Terminal Configuration and Functions
39
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Product Folder Links: TMS320F28379D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D



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