SC2597

9

VTT Output

VTT starts to ramp up when EN and VDD meet their startup

thresholds. SC2597 regulates VTT to the voltage at VREF

and can support up to 3A for sourcing or sinking

capability.

To achieve tight regulation and fast dynamic response at

VTT, it is recommended to connect the VTTS sense signal

to VTT at the ceramic output capacitors.

VREF Output

VREF starts to ramp up when VDD meets the UVLO thresh-

old. SC2597 regulates VREF to one-half of VDDQ. To

reduce the component count and provide a good accu-

racy reference for VTT, SC2597 includes an internal resistor

divider network. SC2597 is capable of sinking or sourcing

up to 60mA at VREF. To reduce the component count

further, SC2597 does not require the user to have a local

ceramic capacitor at the VREF pin - but it is recommended

to layout with a capacitor place holder.

EN Input

The EN pin is used to enable and disable VTT only; it does

not control VREF. When EN is pulled low, the VTT output is

Protection

SC2597 has thermal protection with auto-restart. When

the junction temperature is above the thermal shutdown

remains present. When the junction temperature drops

will be enabled again.

SC2597 has a built-in current limit feature to prevent

damage to the sink and source FETs. If VTT is shorted to

VDD or ground, SC2597 will sink or source current up to

the current limit threshold.

Input Capacitor

The primary purpose of input capacitance is to provide the

charge to the VTT output capacitor when there is a load

transient at VTT. In the typical application circuit, VDDQ

equals VIN, and VTT equals one-half of VDDQ. As a result,

theory tells us that the input capacitance can be chosen to

be half of the output capacitance.

Ceramic capacitors have a capacitance value that degrades

with temperature, DC and AC bias, and their chemistry.

Usually, ceramic capacitors need to be derated by 50%

when operated at their rated DC voltage. Therefore, it is

recommended to use capacitors with a voltage rating of

6.3V or higher for 3.3V or lower applications.

Stability and VTT Capacitor

Figure 1 shows the small signal model for the sourcing

current loop stability. The low frequency pole is formed

by C

OUT

and R

L

. Since this pole depends on those variables,

it is recommended to have a minimum of 10uF C

OUT

for

stable condition. SC2597 has an internal compensation

network to ensure the stability as the load changes. Figure

2 shows the bode plot with the crossover frequency at

around 0.8MHz and 36 degree phase margin. Another

parameter effecting to the loop stability is parasitic induc-

tance in PCB layout and output capacitor ESL. The gain

plot shows that a peaking rising after the crossing fre-

quency is due to ESL effect. Minimizing the ESL reduces

this peaking.

PCB Layout

The SC2597 requires minimal external components to

provide a VTT solution. Figure 3 shows the component

placement and layout for the application circuit on page

6.

Applications Information

VIN

VR EF

VT T

+

-

+

-

Figure 1 — Small Signal Model