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TLE6711 Datasheet(PDF) 12 Page - Infineon Technologies AG |
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TLE6711 Datasheet(HTML) 12 Page - Infineon Technologies AG |
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12 / 28 page ![]() TLE 6711 Circuit Description Data Sheet V 2.22 12 2001-04-23 2 Circuit Description Below some important sections of the TLE 6711 are described in more detail. 2.1 Power On Reset In order to avoid any system failure, a sequence of several conditions has to be passed. In case of V CC power down (VCC < VRT for t > tRR) a logic LOW signal is generated at the pin RO to reset an external microcontroller. When the level of V CC reaches the reset threshold V RT, the signal at RO remains LOW for the Power-up reset delay time tRD beforeswitchingtoHIGH. If V CC drops below the reset threshold VRT for a time extending the reset reaction time t RR, the reset circuit is activated and a power down sequence of period t RD is initiated. The reset reaction time tRR avoids wrong triggering caused by short “glitches” on the V CC-line. Figure 3 Reset Function 2.2 Watchdog Operation The watchdog uses one hundred of the oscillator’s clock signal period as a timebase, defined as the watchdog cycle time t CYL. After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay time t RD, i.e. 64 cycles. With the LOW to HIGH transition of the signal at RO the device starts the closed window time t CW = 32 cycles. A trigger signal within this window is interpreted as a pretrigger failure according to the figures shown below. After the closed window the open window with the duration t OW is started. The open AET02950 L H RO VCC Invalid RT V typ. 4.65 V < RR t < RD t Start-Up ON Delay Invalid Invalid ON Delay Started Stopped RD t RR t RD t t t Power Start-Up Normal Failed N Failed Normal 1 V ON Delay |
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